Hybrid high-k first and high-k last replacement gate process

1. A process of forming an integrated circuit, comprising the steps:

providing a partially processed wafer of the integrated circuit;

growing a high quality first gate dielectric on the partially processed wafer at a temperature of 850° C. or greater;

depositing a high-k first gate dielectric on the high quality first gate dielectric;

forming an NMOS polysilicon replacement gate of a replacement gate NMOS transistor on the high-k first gate dielectric;

forming a PMOS polysilicon replacement gate of a replacement gate PMOS transistor on the high-k first gate dielectric;

depositing a premetal dielectric over the replacement gate NMOS transistor and over the replacement gate PMOS transistor;

planarizing the premetal dielectric to expose a top of the PMOS polysilicon replacement gate and to expose a top of the NMOS polysilicon replacement gate;

forming an NMOS transistor photo resist pattern wherein the NMOS transistor photo resist pattern covers the NMOS polysilicon replacement gate and exposes the PMOS polysilicon replacement gate;

removing the PMOS polysilicon replacement gate to form a PMOS replacement gate transistor trench;

removing the high-k first gate dielectric and removing the high quality first gate dielectric from a bottom of the PMOS replacement gate trench;

removing the NMOS transistor photo resist pattern;

forming a second gate dielectric layer on the integrated circuit wherein the second gate dielectric covers the bottom of the PMOS replacement gate trench;

depositing a high-k last gate dielectric on the integrated circuit;

depositing PMOS metal gate material on the high-k last gate dielectric;

forming a PMOS transistor photo resist pattern wherein the PMOS photo resist pattern covers the PMOS transistor and exposes the NMOS transistor region;

etching the PMOS metal gate material from the NMOS transistor region;

etching the high-k last gate dielectric layer from the NMOS transistor region;

etching the NMOS polysilicon replacement gate to form an NMOS replacement gate transistor trench;

removing the PMOS transistor photo resist pattern;

depositing NMOS metal gate material on the integrated circuit and into the NMOS replacement gate trench; and

polishing the integrated circuit to remove the NMOS and the PMOS metal gate material from a surface of the premetal dielectric and to form an NMOS metal gate in the NMOS replacement gate trench and to form a PMOS metal gate in the PMOS replacement gate trench.

2. The process of claim 1 , wherein the high quality first gate dielectric is silicon dioxide with a thickness in the range of 0.5 to 1.5 nm and wherein the second gate dielectric is SiO x chemically grown with SC1 to a thickness of about 0.6 nm.

3. The integrated circuit of claim 1 , wherein the high-k first gate dielectric is selected from the group consisting of HfO x , HfSiO x , HfSiON, ZrO 2 , HfZrO x , AlO x , or TiO x and wherein the high-k last gate dielectric is selected from the group consisting of HfO x , HfSiO x , HfSiON, ZrO 2 , HfZrO x , AlO x , or TiO x .

4. The integrated circuit of claim 1 , wherein the NMOS metal gate material is selected from the group consisting of titanium, aluminum, titanium-aluminum alloy, and tungsten and wherein the PMOS metal gate material is selected from the group consisting of titanium nitride, tantalum nitride, aluminum, and platinum.

5. The integrated circuit of claim 1 , wherein

the high quality gate dielectric is nitrided silicon dioxide with a thickness in the range of about 0.5 to 1.5 nm;

the high-k first gate dielectric is HfO x with a thickness in the range of about 1 to 3 nm;

the NMOS metal gate material is titanium-aluminum alloy with a thickness of about 3 nm

the second gate dielectric layer is chemically grown with SC1 with a thickness of about 0.6 nm

the high-k last gate dielectric is HfO x with a thickness in the range of about 1 to 3 nm; and

the PMOS metal gate material is titanium nitride with a thickness in the range of about 8 nm.