Carrier for a semiconductor layer
A carrier for carrying a semiconductor layer having a growth surface and at least one nano-patterned structure on the growth surface is provided. The at least one nano-patterned structure on the growth surface of the carrier has a plurality of mesas, a recess is formed between two adjacent mesas, in which a depth of the recess ranges from 10 nm to 500 nm, and a dimension of the mesa ranges from 10 nm to 800 nm.
1. A light emitting diode comprising:
a growth substrate, wherein the growth substrate having a growth surface and at least one nano-patterned structure on the growth surface, the at least one nano-patterned structure comprises a plurality of mesas, a recess is formed between two adjacent mesas, and a depth of the recess ranges from 10 nm to 500 nm, and a dimension of the mesa ranges from 10 nm to 800 nm;
a n-type semiconductor layer disposed on the growth substrate;
an active layer disposed on a portion of the n-type semiconductor layer, and a wavelength λ of light emitted by the active layer is 222 nm≦λ≦405 nm, the active layer comprising i quantum barrier layers and (i−1) quantum wells, each of the quantum wells is disposed between any two quantum barrier layers, and i is a natural number greater than or equal to 2, wherein a n-type dopant is doped in at least k layers of the quantum barrier layers, k being a natural number greater than or equal to 1, when i is an even number, k≧i/2, and when i is an odd number, k≧(i−1)/2;
a p-type semiconductor layer disposed on the active layer; and
a first electrode and a second electrode, wherein the first electrode is disposed on a portion of the n-type semiconductor layer, and the second electrode is disposed on a portion of the p-type semiconductor layer.
2. The light emitting diode according to claim 1 , wherein the mesas of the at least one nano-patterned structure are arranged regularly.
3. The light emitting diode according to claim 1 , wherein the mesas of the at least one nano-patterned structure are arranged randomly.
4. The light emitting diode according to claim 1 , wherein a dimension w 1 of the mesa and a dimension w 2 of the recess satisfy the following relationship:
0.0125≦[w 1 /w 2 ]≦80.
5. The light emitting diode according to claim 1 , wherein a plurality of voids are formed above the recesses or above the mesas between the growth substrate and the n-type semiconductor layer.
6. The light emitting diode according to claim 5 , wherein each of the voids has a refraction coefficient n 2 , the growth substrate has a refraction coefficient n 1 and the n-type semiconductor layer has a refraction coefficient n 3 , where n 3 >n 2 >n 1 .
7. The light emitting diode according to claim 1 , further comprising:
a mask layer, covering sidewalls of each mesa and a bottom surface of each recess between the two adjacent mesas.
8. The light emitting diode according to claim 7 , wherein a thickness of the mask layer ranges from 0.1 μm to 2 μm.
9. The light emitting diode according to claim 7 , wherein a material of the mask layer comprises silicon dioxide, silicon nitride or silicon oxynitride.
10. The light emitting diode according to claim 1 , wherein
a doping concentration of the quantum barrier layer in the k quantum barrier layers nearest to the p-type semiconductor layer being less than the doping concentration of the other quantum barrier layers in the k quantum barrier layers.
11. A light emitting diode, comprising:
a growth substrate, wherein the growth substrate having a growth surface and at least one nano-patterned structure on the growth surface, the at least one nano-patterned structure comprises a plurality of mesas, a recess is formed between two adjacent mesas, and a depth of the recess ranges from 10 nm to 500 nm, and a dimension of the mesa ranges from 10 nm to 800 nm;;
an n-type semiconductor layer and a p-type semiconductor layer, wherein the n-type semiconductor layer is located between the growth substrate and the p-type semiconductor layer;
an active layer located between the n-type semiconductor layer and the p-type semiconductor layer, wherein a wavelength of light emitted by the active layer is λ, 222 nm ≦λ≦405 nm, the active layer includes i quantum barrier layers and (i−1) quantum wells, each of the quantum wells is located between any two of the quantum barrier layers, i is a natural number greater than or equal to 2, a thickness of each of the quantum barrier layers, counting from the p-type semiconductor layer, is T 1 , T 2 , T 3 . . . , and T i in sequence, and T 1 is greater than T 2 and T 3 ; and
a first electrode and a second electrode, wherein the first electrode is located on a portion of the n-type semiconductor layer, and the second electrode is located on a portion of the p-type semiconductor layer.
12. A light emitting diode, comprising:
a growth substrate, wherein the growth substrate having a growth surface and at least one nano-patterned structure on the growth surface, the at least one nano-patterned structure comprises a plurality of mesas, a recess is formed between two adjacent mesas, and a depth of the recess ranges from 10 nm to 500 nm, and a dimension of the mesa ranges from 10 nm to 800 nm;
an n-type semiconductor layer and a p-type semiconductor layer, wherein the n-type semiconductor layer is located between the growth substrate and the p-type semiconductor layer;
an active layer, located between the n-type semiconductor layer and the p-type semiconductor layer, wherein a wavelength of light emitted by the active layer is λ, 222 nm≦λ≦405 nm, the active layer comprises i quantum barrier layers and (i−1) quantum wells, each of the quantum wells is located between any two of the quantum barrier layers, where i is a natural number greater than or equal to 2, and a lattice constant of the quantum barrier layer closest to the p-type semiconductor layer among the quantum barrier layers is a 1 ;
an interlayer, located between the active layer and the p-type semiconductor layer, and in contact with the quantum barrier layer closest to the p-type semiconductor layer, wherein a lattice constant of the interlayer is a 2 ;
an electron barrier layer, located between the interlayer and the p-type semiconductor layer, and in contact with the interlayer and the p-type semiconductor layer, wherein a lattice constant of the electron barrier layer is a 3 , and a 2 is not equal to a 1 and a 3 ; and
a first electrode and a second electrode, wherein the first electrode is located on a portion of the n-type semiconductor layer, and the second electrode is located on a portion of the p-type semiconductor layer.