Programmable hysteresis comparator
In one embodiment, a circuit includes a differential amplifier having a differential pair with a first transistor and second transistor. Each of the first and the second transistors include a front gate contact and a back gate contact. A first digital feedback loop is coupled between an output of the differential amplifier to the back gate contact of the first transistor. A second digital feedback loop is coupled to the back gate contact of the second transistor. The first digital feedback loop is configured to be opposite in phase to the second digital feedback loop.
1. A circuit comprising:
a differential amplifier comprising a differential pair comprising a first transistor and second transistor, each of the first and the second transistors comprising a front gate contact and a back gate contact;
an inverting circuit having an input and an output, wherein the input of the inverting circuit is coupled to an output of the differential amplifier;
a first node between the input of the inverting circuit and the output of the differential amplifier;
a second node coupled to the output of the inverting circuit;
a first digital feedback loop coupled between the first node and the back gate contact of the first transistor; and
a second digital feedback loop coupled between the second node and the back gate contact of the second transistor, wherein the first digital feedback loop is configured to be opposite in phase to the second digital feedback loop.
2. The circuit of claim 1 , wherein the circuit is a comparator.
3. The circuit of claim 2 , wherein the comparator is one of a CMOS op amp, a folded cascoded comparator, clamped voltage comparator.
4. The circuit of claim 1 , further comprising:
a common source amplifier coupled to the output of the differential amplifier.
5. The circuit of claim 1 , further comprising:
a common source amplifier coupled to the output of the differential amplifier; and
an inverter coupled to the output of the common source amplifier.
6. The circuit of claim 1 , wherein the differential pair is unbalanced.
7. The circuit of claim 1 , further comprising:
a current mirror load coupled to the differential pair, the current mirror comprising a third transistor and a fourth transistor, each of the third and the fourth transistors comprising a front gate contact and a back gate contact;
a third digital feedback loop coupled to the back gate contact of the third transistor; and
a fourth digital feedback loop coupled to the back gate contact of the fourth transistor, wherein the third digital feedback loop is configured to be opposite in phase to the fourth digital feedback loop.
8. The circuit of claim 7 , wherein the third transistor is coupled to the first transistor and the fourth transistor is coupled to the second transistor, wherein the third digital feedback loop and the first digital feedback loop are configured to provide the same feedback signal, and wherein the fourth digital feedback loop and the second digital feedback are configured to provide the same feedback signal.
9. A circuit comprising:
a current mirror comprising a first transistor and second transistor, each of the first and the second transistors comprising a front gate contact and a back gate contact, wherein the front gate contact of the first transistor is coupled to the front gate contact of the second transistor;
a first digital feedback loop coupled to the back gate contact of the first transistor; and
a second digital feedback loop coupled to the back gate contact of the second transistor, wherein the first digital feedback loop is configured to be opposite in phase to the second digital feedback loop.
10. The circuit of claim 9 , further comprising a differential transistor pair coupled to the current mirror.
11. The circuit of claim 9 , wherein the circuit is a comparator.
12. The circuit of claim 11 , wherein the comparator is one of a CMOS op amp, a folded cascoded comparator, clamped voltage comparator.
13. A comparator comprising:
a differential amplifier including a differential transistor pair comprising a first transistor and a second transistor, wherein each of the first and the second transistors comprise a four terminal silicon on insulator transistor comprising a back gate contact;
a first inverter coupled to an output of the differential amplifier;
a first feedback loop coupled between an output of the first inverter and the back gate contact of the first transistor;
a second inverter coupled to the output of the first inverter; and
a second feedback loop coupled between the output of the second inverter and the back gate contact of the second transistor.
14. The comparator of claim 13 , further comprising a common source amplifier coupled to the output of the differential amplifier, wherein the first inverter is coupled to an output of the common source amplifier.
15. The comparator of claim 13 , further comprising:
a common source amplifier coupled to an output of the differential amplifier; and
a third inverter coupled to an output of the common source amplifier, wherein the first inverter is coupled to an output of the third inverter.
16. The comparator of claim 13 , further comprising a current mirror coupled to the differential transistor pair.
17. The comparator of claim 13 , wherein the four terminal silicon on insulator transistor of the differential transistor pair is a fully depleted silicon on insulator transistor.
18. A comparator comprising:
a differential amplifier including a current mirror comprising a first transistor and a second transistor, wherein each of the first and the second transistors comprise a four terminal silicon on insulator transistor comprising a back gate contact;
a first inverter coupled to an output of the differential amplifier;
a first feedback loop coupled between an output of the first inverter and the back gate contact of the first transistor;
a second inverter coupled to the output of the first inverter; and
a second feedback loop coupled between an output of the second inverter and the back gate contact of the second transistor.
19. The comparator of claim 18 , further comprising a common source amplifier coupled to the output of the differential amplifier, wherein the first inverter is coupled to the output of an common source amplifier.
20. The comparator of claim 18 , further comprising:
a common source amplifier coupled to the output of the differential amplifier; and
a third inverter coupled to an output of the common source amplifier, wherein the first inverter is coupled to an output of the third inverter.
21. A method of operating a comparator circuit, the method comprising:
providing a transistor pair comprising a first transistor and a second transistor, wherein the first and the second transistors comprise a four terminal comprising a front gate contact and a back gate contact;
generating a first digital feedback signal from an output of the transistor pair;
generating a second digital feedback signal by inverting the first feedback signal; and
changing a hysteresis of the comparator circuit by applying the first digital feedback signal on the back gate contact of the first transistor and the second digital feedback signal on the back gate contact of the second transistor, wherein the first feedback signal is opposite in phase to the second feedback signal.
22. The method of claim 21 , wherein the transistor pair is a silicon on insulator technology.
23. The method of claim 21 , wherein the transistor pair is a fully depleted silicon on insulator technology.
24. The method of claim 21 , wherein the transistor pair is a differential transistor pair.
25. The method of claim 21 , wherein the transistor pair is a current mirror.
26. The circuit of claim 1 , wherein the inverting circuit is an inverter.
27. The comparator of claim 13 , further comprising:
a first programmable switch between the output of the first inverter and the back gate contact of the first transistor, the first programmable switch configured to apply the first feedback loop at the back gate contact of the first transistor; and
a second programmable switch coupled between the output of the second inverter and the back gate contact of the second transistor, the second programmable switch configured to apply the second feedback loop at the back gate contact of the second transistor.
28. The comparator of claim 27 , wherein the differential amplifier includes another differential transistor pair comprising a third transistor and a fourth transistor, wherein each of the third and the fourth transistors comprise a four terminal silicon on insulator transistor comprising a back gate contact;
a third feedback loop coupled between the output of the first inverter and the back gate contact of the third transistor, wherein the third feedback loop comprises the same signal as the first feedback loop; and
a fourth feedback loop coupled between the output of the second inverter and the back gate contact of the fourth transistor, wherein the fourth feedback loop comprises the same signal as the second feedback loop.
29. The comparator of claim 28 , wherein the first programmable switch is configured to apply the third feedback loop at the back gate contact of the third transistor, wherein the second programmable switch is configured to apply the fourth feedback loop at the back gate contact of the fourth transistor.
30. The comparator of claim 18 , further comprising:
a first programmable switch between the output of the first inverter and the back gate contact of the first transistor, the first programmable switch configured to apply the first feedback loop at the back gate contact of the first transistor; and
a second programmable switch coupled between the output of the second inverter and the back gate contact of the second transistor, the second programmable switch configured to apply the second feedback loop at the back gate contact of the second transistor.
31. The comparator of claim 30 , wherein the differential amplifier includes another differential transistor pair comprising a third transistor and a fourth transistor, wherein each of the third and the fourth transistors comprise a four terminal silicon on insulator transistor comprising a back gate contact;
a third feedback loop coupled between the output of the first inverter and the back gate contact of the third transistor, wherein the third feedback loop comprises the same signal as the first feedback loop; and
a fourth feedback loop coupled between the output of the second inverter and the back gate contact of the fourth transistor, wherein the fourth feedback loop comprises the same signal as the second feedback loop.
32. The comparator of claim 31 , wherein the first programmable switch is configured to apply the third feedback loop at the back gate contact of the third transistor, wherein the second programmable switch is configured to apply the fourth feedback loop at the back gate contact of the fourth transistor.