Operand fetching control as a function of branch confidence

1. A computer program product for operand fetching control in a computer processor pipeline of a processor having a data cache to store operands fetched by load/store instructions, the computer program product comprising:

a tangible, non-transitory storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:

calculating a summation weight value for each instruction or group of instructions in the computer processor pipeline, the summation weight value calculated as a function of branch uncertainty and a pendency in which the instruction or group of instructions reside in the computer processor pipeline relative to other instructions in the computer processor pipeline;

mapping, by a control unit logic of the computer processor pipeline, the summation weight value of a selected load/store instruction in the computer processor pipeline that is attempting to access system memory to one of a number of distinct pre-defined ranges of summation weight values, each of the pre-defined ranges of summation weight values corresponding to a respective memory access control, each of the memory access controls specifying a different manner of handling an operand fetching operation from the data cache, wherein each manner of handling defines a respective depth in a cache hierarchy of the data cache that an operand fetch is permitted to access;

receiving the mapped memory access control for the selected load/store instruction from the control unit logic by a load-store unit of the computer processor pipeline via an interface between the control unit logic and the load-store unit; and

performing a memory access operation for the selected load/store instruction based on the manner of handling the operand fetching operation that is specified by the received mapped memory access control by the load-store unit.

2. The computer program product of claim 1 , wherein the method further comprises:

tracking the summation weight values,

wherein calculating the summation weight value as a function of the branch uncertainty comprises:

for each instruction or group of instructions in the computer processor pipeline, summing an uncertainty value assigned to a corresponding instruction with a summation value representing a cumulative sum of uncertainty values assigned to all older instructions in the computer processor pipeline.

3. The computer program product of claim 1 , wherein the method further comprises:

calculating an uncertainty value that represents the branch confidence for each branch instruction or group of instructions that include the branch instruction in the computer processor pipeline, the uncertainty value calculated as a function of branch prediction logic and programmable options that include factors used in weighting predictions based on prediction type.

4. The computer program product of claim 3 , wherein the method further comprises:

modifying an uncertainty value assigned to the branch instruction upon resolution of the branch instruction in the computer processor pipeline, the uncertainty value modified to reflect a high branch prediction confidence.

5. The computer program product of claim 1 , wherein the method further comprises:

re-calculating, at each clock cycle, the summation weight value for each instruction or group of instructions, the re-calculating comprising:

summing an uncertainty value assigned to a corresponding branch instruction with a summation value representing a cumulative sum of uncertainty values assigned to all older instructions in the computer processor pipeline.

6. The computer program product of claim 1 , wherein the memory access controls comprise a first manner of handling the operand fetching operation from the data cache comprising:

permitting the load-store unit of the computer processor pipeline to fetch an operand from the data cache according to default memory access processing based on the mapping received via the interface corresponding to the summation weight value being within a first range of summation weight values.

7. The computer program product of claim 1 , wherein the memory access controls comprise a second manner of handling the operand fetching operation from the data cache comprising:

permitting the load-store unit of the computer processor pipeline to fetch an operand from a secondary level of the data cache, and

blocking the load-store unit of the computer processor pipeline from fetching the operand from a tertiary level of the data cache when the operand is not found in the secondary level of the data cache based on the mapping received via the interface corresponding to the summation weight value being within a second range of summation weight values;

wherein the secondary level of the data cache is a level of the data cache that is located further away from a processor than a first level of the data cache, and the tertiary level of the data cache is a level of the data cache that is located further away from the processor than the secondary level of the data cache.

8. The computer program product of claim 1 , wherein the memory access controls comprise a third manner of handling the operand fetching operation from the data cache of the computer processor pipeline comprising:

permitting the load-store unit of the computer processor pipeline to access a secondary level of the data cache; and

preventing logic of the secondary level of cache from processing an operand fetch from the secondary level of the data cache based on the mapping received via the interface corresponding to the summation weight value being within a third range of summation weight values.

9. The computer program product of claim 1 , wherein the method further comprises:

canceling, by the load-store unit based on a cancel command received via the interface from the control unit logic, a fetch request associated with the branch instruction when data subject to the fetch request is determined to be non-demand data; wherein the data is determined to be non-demand data when the data is not needed for execution of a program issuing the fetch request.

10. The computer program product of claim 1 , wherein the interface between the control unit logic and the load-store unit comprises a 2-bit interface, and wherein the number of pre-defined ranges of summation weight values is three.

11. A system for operand fetching control in a computer processor pipeline, the system comprising:

a computer processor comprising a control unit for determining memory access operations and a data cache to store operands fetched by load/store instructions; the control unit configured to perform a method, the method comprising:

calculating a summation weight value for each instruction or group of instructions in the computer processor pipeline, the summation weight value calculated as a function of branch uncertainty and a pendency in which the instruction or group of instructions reside in the computer processor pipeline relative to other instructions in the computer processor pipeline;

mapping, by a control unit logic of the computer processor pipeline, the summation weight value of a selected load/store instruction in the computer processor pipeline that is attempting to access system memory to one of a number of distinct pre-defined ranges of summation weight values, each of the pre-defined ranges of summation weight values corresponding to a respective memory access controls, each of the memory access controls specifying a different manner of handling an operand fetching operation from the data cache, wherein each manner of handling defines a respective depth in a cache hierarchy of the data cache that an operand fetch is permitted to access;

receiving the mapped memory access control for the selected load/store instruction from the control unit logic by a load-store unit of the computer processor pipeline via an interface between the control unit logic and the load-store unit; and

performing a memory access operation for the selected load/store instruction based on the manner of handling the operand fetching operation that is specified by the received mapped memory access control by the load-store unit.

12. The system of claim 11 , wherein the method further comprises:

tracking the summation weight values;

wherein calculating the summation weight value as a function of the branch confidence comprises:

for each instruction or group of instructions in the computer processor pipeline, summing an uncertainty value assigned to a corresponding instruction with a summation value representing a cumulative sum of uncertainty values assigned to all older instructions in the computer processor pipeline.

13. The system of claim 11 , wherein the method further comprises:

calculating an uncertainty value that represents the branch confidence for each branch instruction or group of instructions that include the branch instruction in the computer processor pipeline, the uncertainty value calculated as a function of branch prediction logic and programmable options that include factors used in weighting predictions based on prediction type.

14. The system of claim 13 , wherein the method further comprises:

modifying an uncertainty value assigned to the branch instruction upon resolution of the branch instruction in the computer processor pipeline, the uncertainty value modified to reflect a high branch prediction confidence.

15. The system of claim 11 , wherein the method further comprises:

re-calculating, at each clock cycle, the summation weight value for each instruction or group of instructions, the re-calculating comprising:

summing an uncertainty value assigned to a corresponding branch instruction with a summation value representing a cumulative sum of uncertainty values assigned to all older instructions in the computer processor pipeline.

16. The system of claim 11 , wherein the memory access controls comprise a first manner of handling the operand fetching operation from the data cache comprising:

permitting the load-store unit of the computer processor pipeline to fetch an operand from the data cache according to default memory access processing based on the mapping received via the interface corresponding to the summation weight value being within a first range of summation weight values.

17. The system of claim 11 , wherein the memory access controls comprise a second manner of handling the operand fetching operation from the data cache comprising:

permitting the load-store unit of the computer processor pipeline to fetch an operand from a secondary level of the data cache, and

blocking the load-store unit of the computer processor pipeline from fetching the operand from a tertiary level of the data cache when the operand is not found in the secondary level of the data cache based on the mapping received via the interface corresponding to the summation weight value being within a second range of summation weight values;

wherein the secondary level of the data cache is a level of the data cache that is located further away from a processor than a first level of the data cache, and the tertiary level of the data cache is a level of the data cache that is located further away from the processor than the secondary level of the data cache.

18. The system of claim 11 , wherein the memory access controls comprise a third manner of handling the operand fetching operation from the data cache comprising:

permitting the load-store unit of the computer processor pipeline to access a secondary level of the data cache; and

preventing logic of the secondary level of cache from processing an operand fetch from the secondary level of the data cache based on the mapping received via the interface corresponding to the summation weight value being within a third range of summation weight values.

19. The system of claim 11 , wherein the method further comprises:

canceling, by the load-store unit based on a cancel command received via the interface from the control unit logic, a fetch request associated with the branch instruction when data subject to the fetch request is determined to be non-demand data; wherein the data is determined to be non-demand data when the data is not needed for execution of a program issuing the fetch request.

20. The system of claim 11 , wherein the interface between the control unit logic and the load-store unit comprises a 2-bit interface, and wherein the number of pre-defined ranges of summation weight values is three.