System, method and apparatus for improving transactional memory (TM) throughput using TM region indicators

1. An apparatus comprising:

logic to assign a transactional memory (TM) region indicator to each instruction of a transaction;

execution logic to execute each instruction of the transaction;

a copy-on-write (COW) buffer to maintain a mapping from checkpointed architectural registers to physical registers, wherein the COW buffer to maintain a plurality of register checkpoints for a plurality of TM regions by marking separations between TM regions using pointers, a first pointer to identify a position in the COW buffer of the last committed instruction, a retirement pointer to identify a boundary between a youngest TM region and a currently retiring instruction position;

a data cache to store data associated with executed instructions, wherein each entry of the data cache has a read-bit per TM region indicator to mark memory state of speculative reads wherein a read-bit for a TM region is set when data is speculatively read from that cache line during that transaction and a write-bit to indicate when the cache line has speculatively written data.

2. The apparatus of claim 1 , wherein the logic to assign a transactional memory (TM) region indicator to each instruction of a transaction is allocation logic.

3. The apparatus of claim 1 , wherein each of the first, second, and retirement pointers are stored in dedicated registers.

4. The apparatus of claim 1 , wherein when the transaction commits, read-bits associated with that transaction are cleared.

5. The apparatus of claim 1 , wherein when the transaction aborts, read-bits associated with that transaction are cleared and read-bits for any transaction younger than the transaction are also cleared.

6. The apparatus of claim 1 , wherein when the transaction commits, write-bits associated with that transaction are cleared.

7. The apparatus of claim 1 , wherein read-bits and write-bits associated with a data cache line are stored in the data cache.

8. A method comprising:

assigning a transactional memory (TM) region indicator to each instruction of a transaction;

storing previously used physical registers associated with the transaction into a copy-on-write (COW) buffer, wherein the COW maintains a plurality of register checkpoints for a plurality of TM regions by marking separations between TM regions using pointers, a first pointer to identify a position in the COW of the last committed instruction, and a retirement pointer to identify a boundary between a youngest TM region and a currently retiring position;

executing the instructions of the transaction;

retiring one or more oldest load instructions of each TM region from a reorder buffer until a first instruction of an oldest TM region that is not in an initial grouping from that TM region is reached until the oldest TM region has committed; and

setting a read-bit for each load that has been retired into a corresponding data cache entry.

9. The method of claim 8 , wherein the assigning occurs during an allocation stage of a pipeline.

10. The method of claim 8 , wherein the load instructions are retired from a reorder buffer.

11. The method of claim 8 , further comprising:

determining that the transaction is to commit;

committing the transaction;

freeing the previously used physical registers associated with the transaction from the COW buffer; and

clearing read-bits associated with the transaction from the data cache.

12. The method of claim 8 , further comprising:

determining that the transaction is to not commit;

rolling back to a previous state using the physical registers associated with the transaction from the COW buffer;

freeing the previously used physical registers associated with the transaction from the COW buffer; and

clearing read-bits associated with the transaction from the data cache and any read-bits of cache lines that are younger than the transaction.

13. The method of claim 8 , wherein the beginning of the transaction is indicated by an instruction.

14. The method of claim 8 , wherein the end of the transaction is indicated by an instruction.

15. A method comprising:

assigning a transactional memory (TM) region indicator to each instruction of a transaction;

executing each instruction of the transaction;

retiring one or more store instructions of the transaction from a store buffer until a last store instruction of an oldest TM region of a plurality of TM regions is retired and halting retirement of any other store instructions until the oldest TM region has committed; and

setting a write-bit for each store instruction that has been retired into a corresponding entry of a data cache.

16. The method of claim 15 , wherein the assigning occurs during an allocation stage of a pipeline.

17. The method of claim 15 , further comprising:

determining that the transaction is to commit;

committing the transaction;

clearing write-bits associated with the transaction from the data cache.

18. The method of claim 15 , further comprising:

determining that the transaction is to not commit;

rolling back to a previous state by discarding store instructions that were speculatively written into the data cache.

19. The method of claim 15 , wherein the transaction is indicated by a beginning and an ending instruction.