Data write control device and data storage device
According to one embodiment, a data transfer control device complying with a communication protocol which executes an update of information from an attachment device in a predetermined area of a system memory, the device includes a receiving part receiving the information from the attachment device, a transferring part transferring the information in the predetermined area, the information from the transferring part overwritten in the predetermined area sequentially, and a determining part inhibiting a transfer of the information in the transferring part to omit the update of the information in the predetermined area.
1. A memory system connectable to a host, the memory system comprising:
a nonvolatile memory; and
a controller controlling the nonvolatile memory, the controller being configured to:
receive a first write command from the host, the first write command requesting for guaranteeing that a first write data is written to the nonvolatile memory;
queue a second write command being associated with the first write command in a queuing part;
receive a third write command from the host, the third write command requesting for guaranteeing that a second write data is written to the nonvolatile memory;
queue a fourth write command being associated with the third write command in the queuing part;
store the first write data in a buffer memory;
store the second write data in the buffer memory;
transfer the first write data and the second write data in series from the buffer memory to the nonvolatile memory when a predetermined condition is complied with;
send a first reply to the host after receiving a second reply from the nonvolatile memory, the second reply being sent from the nonvolatile memory when the first write data is stored in the nonvolatile memory, the first reply being associated with the second reply, the first reply being a response of the first write command; and
send a third reply to the host after receiving a fourth reply from the nonvolatile memory, the fourth reply being sent from the nonvolatile memory when the second write data is stored in the nonvolatile memory, the third reply being associated with the fourth reply, the third reply being a response of the third write command.
2. The system of claim 1 ,
wherein the predetermined condition is that both the first and second write data is stored in the buffer memory.
3. The system of claim 2 ,
wherein the first and second write commands are deleted from the queuing part when both the first and second write data are stored in the buffer memory.
4. The system of claim 3 ,
wherein the first and second write data are not transferred to the nonvolatile memory before both the first and second write data are stored in the buffer memory.
5. The system of claim 3 ,
wherein the predetermined condition is that a fixed period elapses after the second and fourth write commands are deleted from the queuing part, in a case where a new command is not queued in the queuing part in the fixed period.
6. The system of claim 5 , comprising:
a timer configured to measure the fixed period.
7. The system of claim 3 ,
wherein the predetermined condition is that a fixed period elapses after the second and fourth write commands are deleted from the queuing part, in a case where a new command may be queued in the queuing part in the fixed period.
8. The system of claim 1 ,
wherein the buffer memory is a static random access memory (SRAM).
9. The system of claim 1 ,
wherein the predetermined condition is that a number of commands including the second and fourth write commands are larger than a threshold value.
10. The system of claim 1 ,
wherein the predetermined condition is that a total size of data associated with commands including the second and fourth write commands is larger than a threshold value.
11. A memory system connectable to a host, the memory system comprising:
a nonvolatile memory;
a buffer memory; and
a controller controlling the nonvolatile memory and the buffer memory, the controller being configured to:
receive a first write command from the host, the first write command requesting for guaranteeing that a first write data is written to the nonvolatile memory;
queue a second write command being associated with the first write command in a queuing part;
receive a third write command from the host, the third write command requesting for guaranteeing that a second write data is written to the nonvolatile memory;
queue a fourth write command being associated with the third write command in the queuing part;
store the first write data in the buffer memory;
store the second write data in the buffer memory;
transfer the first write data and the second write data in series from the buffer memory to the nonvolatile memory when a predetermined condition is complied with;
send a first reply to the host after receiving a second reply from the nonvolatile memory, the second reply being sent from the nonvolatile memory when the first write data is stored in the nonvolatile memory, the first reply being associated with the second reply, the first reply being a response of the first write command; and
send a third reply to the host after receiving a fourth reply from the nonvolatile memory, the fourth reply being sent from the nonvolatile memory when the second write data is stored in the nonvolatile memory, the third reply being associated with the fourth reply, the third reply being a response of the third write command.
12. The system of claim 11 ,
wherein the predetermined condition is that both the first and second write data are stored in the buffer memory.
13. The system of claim 12 ,
wherein the first and second write commands are deleted from the queuing part when both the first and second write data are stored in the buffer memory.
14. The system of claim 13 ,
wherein the first and second write data are not transferred to the nonvolatile memory before both the first and second write data are stored in the buffer memory.
15. The system of claim 13 ,
wherein the predetermined condition is that a fixed period elapses after the second and fourth write commands are deleted from the queuing part, in a case where a new command is not queued in the queuing part in the fixed period.
16. The system of claim 15 , comprising:
a timer configured to measure the fixed period.
17. The system of claim 13 ,
wherein the predetermined condition is that a fixed period elapses after the second and fourth write commands are deleted from the queuing part, in a case where a new command may be queued in the queuing part in the fixed period.
18. The system of claim 11 ,
wherein the buffer memory is a dynamic random access memory (DRAM).
19. The system of claim 11 ,
wherein the predetermined condition is that a number of commands including the second and fourth write commands are larger than a threshold value.
20. The system of claim 11 ,
wherein the predetermined condition is that a total size of data associated with commands including the second and fourth write commands is larger than a threshold value.