Distributed amplifier with improved stabilization
A distributed amplifier with improved stabilization includes an input transmission circuit, an output transmission circuit, at least one cascade amplifier coupled between said input and output transmission circuits. Each cascade amplifier includes a common-gate configured transistor coupled to the output transmission circuit, and a common-source configured transistor coupled between the input transmission circuit and the common-gate configured transistor. The distributed amplifier also includes a non-parasitic resistance and capacitance coupled in series between a drain and a gate of at least one of the common-gate configured transistors for increasing the amplifier stability.
1. A distributed amplifier comprising:
an input transmission line;
an output transmission line; and
a plurality of cascode amplifiers each coupled between the input transmission line and the output transmission line, wherein a first cascode amplifier of the plurality of cascode amplifiers comprises:
three or more field effect transistors (FETs) arranged in a stack, wherein the three or more FETs comprises a first FET, a second FET, and a third FET, wherein the first FET includes a gate coupled to the input transmission line, wherein the second FET is positioned between the first FET and the third FET in the stack, and wherein the third FET includes a drain coupled to the output transmission line; and
a first stabilization circuit coupled to the drain of the third FET,
wherein the first FET is configured to generate an amplified signal by amplifying an input signal received at the gate of the first FET from the input transmission line, wherein the first FET is further configured to provide the amplified signal to the output transmission line through the second FET, from a source of the second FET to a drain of the second FET, and through the third FET, from a source of the third FET to the drain of the third FET.
2. The distributed amplifier of claim 1 , wherein the first stabilization circuit comprises a first resistor and a first capacitor electrically connected in series.
3. The distributed amplifier of claim 2 , wherein the first resistor and the first capacitor are electrically connected in series between the drain of the third FET and a gate of the third FET.
4. The distributed amplifier of claim 1 , further comprising a second stabilization circuit coupled to a drain of the second FET.
5. The distributed amplifier of claim 4 , wherein the first stabilization circuit comprises a first resistor and a first capacitor electrically connected in series between the drain of the third FET and a gate of the third FET, and wherein the second stabilization circuit comprises a second resistor and a second capacitor electrically connected in series between the drain of the second FET and a gate of the second FET.
6. The distributed amplifier of claim 1 , further comprising a first gate resistor and a first gate capacitor electrically connected in series between a gate of the third FET and a ground node.
7. The distributed amplifier of claim 6 , further comprising a second gate resistor and a second gate capacitor electrically connected in series between a gate of the second FET and the ground node.
8. The distributed amplifier of claim 1 , further comprising a gate line termination coupled to the input transmission line and a drain line termination coupled to the output transmission line.
9. The distributed amplifier of claim 1 , wherein the first stabilization circuit is configured to inhibit parametric oscillations.
10. The distributed amplifier of claim 1 , wherein the plurality of cascode amplifiers comprises between four and ten cascode amplifiers.
11. A distributed amplifier comprising:
an input transmission line;
an output transmission line; and
a plurality of cascode amplifiers each coupled between the input transmission line and the output transmission line, wherein a first cascode amplifier of the plurality of cascode amplifiers comprises:
three or more field effect transistors (FETs) arranged in a stack, wherein the three or more FETs comprises a first FET, a second FET, and a third FET, wherein the first FET includes a gate coupled to the input transmission line, wherein the second FET is positioned between the first FET and the third FET in the stack, and wherein the third FET includes a drain coupled to the output transmission line; and
a first stabilization circuit coupled to a drain of the second FET,
wherein the first FET is configured to generate an amplified signal by amplifying an input signal received at the gate of the first FET from the input transmission line, wherein the first FET is further configured to provide the amplified signal to the output transmission line through the second FET, from a source of the second FET to the drain of the second FET, and through the third FET, from a source of the third FET to the drain of the third FET.
12. The distributed amplifier of claim 11 , wherein the first stabilization circuit comprises a first resistor and a first capacitor electrically connected in series.
13. The distributed amplifier of claim 12 , wherein the first resistor and the first capacitor are electrically connected in series between the drain of the second FET and a gate of the second FET.
14. The distributed amplifier of claim 11 , further comprising a gate line termination coupled to the input transmission line and a drain line termination coupled to the output transmission line.
15. A distributed amplifier comprising:
an input transmission line;
an output transmission line; and
a plurality of cascode amplifiers each coupled between the input transmission line and the output transmission line, wherein a first cascode amplifier of the plurality of cascode amplifiers comprises:
three or more field effect transistors (FETs) arranged in a stack, wherein the three or more FETs comprises a first FET, a second FET, and a third FET, wherein the first FET includes a gate coupled to the input transmission line, wherein the second FET is positioned between the first FET and the third FET in the stack, and wherein the third FET includes a drain coupled to the output transmission line; and
a first stabilization circuit coupled to a gate of the third FET, wherein the first stabilization circuit comprises a first resistor and a first capacitor electrically connected in series,
wherein the first FET is configured to generate an amplified signal by amplifying an input signal received at the gate of the first FET from the input transmission line, wherein the first FET is further configured to provide the amplified signal to the output transmission line through the second FET, from a source of the second FET to a drain of the second FET, and through the third FET, from a source of the third FET to the drain of the third FET.
16. The distributed amplifier of claim 15 , wherein the first resistor and the first capacitor are electrically connected in series between the gate of the third FET and a ground node.
17. The distributed amplifier of claim 15 , further comprising a second stabilization circuit coupled to a gate of the second FET.
18. The distributed amplifier of claim 17 , wherein the second stabilization circuit comprises a second resistor and a second capacitor electrically connected in series.
19. The distributed amplifier of claim 15 , wherein the first resistor has a resistance value in the range of between 20 ohms to 10 K ohms.
20. The distributed amplifier of claim 15 , further comprising a gate line termination coupled to the input transmission line and a drain line termination coupled to the output transmission line.
21. The distributed amplifier of claim 1 , wherein the three or more FETs are electrically connected in series with one another.
22. The distributed amplifier of claim 11 , wherein the three or more FETs are electrically connected in series with one another.
23. The distributed amplifier of claim 15 , wherein the three or more FETs are electrically connected in series with one another.