Substrate for mounting multiple power transistors thereon and power semiconductor module
Exemplary embodiments provide a substrate for mounting multiple power transistors. The substrate has a first metallization on which the power transistors are mountable with an associated collector or emitter, and which extends in at least one line on the substrate. A second metallization extends in an area next to the at least one line of the first metallization, for connection to the remaining ones of the emitters or collectors of the power transistors. A third metallization allows connection to gate contact pads of the power transistors. The third metallization includes a gate contact and at least two gate metallization areas, which are interconnectable. The gate metallization areas are arranged in parallel to the at least one line and spaced apart in a longitudinal direction of the at least one line. At least one gate metallization area is provided as a gate island surrounded on the substrate by the second metallization.
1. A substrate comprising:
multiple power transistors mounted thereon;
a first metallization, on which the power transistors are commonly mountable with their collector or emitter, and which extends in at least one line on the substrate;
a second metallization, which extends in an area next to the at least one line of the first metallization, for connection to other ones of the emitters or collectors of the power transistors; and
a third metallization for connection to gate contact pads of the power transistors, wherein the third metallization includes at least two gate metallization areas, which are interconnectable through bonding means, whereby the gate metallization areas are arranged in parallel to the at least one line and spaced apart in a longitudinal direction of the at least one line;
at least one gate metallization area is provided as a gate island surrounded on the substrate by the second metallization, wherein the second metallization is adapted for mounting multiple power transistors with their collectors or emitters thereon, whereby the power transistors have the same orientation like the power transistors mounted on the first metallization;
a fourth metallization, which extends in an area next to the second metallization, for connection to the other ones of the emitters or collectors of the power transistors mountable on the second metallization; and
a fifth metallization for connection to gate contact pads of the power transistors mountable on the second metallization, wherein the fifth metallization includes at least two gate metallization areas, which are interconnectable by way of bonding means, and the at least two gate metallization areas are arranged in parallel to the at least one line and spaced apart in a longitudinal direction of the at least one line; and
at least one gate metallization area is provided as a gate island surrounded on the substrate by the fourth metallization.
2. The substrate according to claim 1 , wherein the third metallization comprises a gate contact, which is interconnectable with the at least two gate metallization areas by way of bonding means.
3. The substrate according to claim 1 , wherein the length of the at least one gate island in a longitudinal direction of the at least one line is smaller than the extension of the power transistors in that direction.
4. The substrate according to claim 1 , wherein the size of the at least one gate island in a direction perpendicular to the at least one line of the first metallization is between 0.5 mm and 3.0 mm.
5. The substrate according to claim 1 , wherein the size of the at least one gate island in a direction perpendicular to the at least one line of the first metallization is between 1.0 mm and 2.0 mm.
6. The substrate according to claim 1 , wherein the at least two gate metallization areas are located centrally in the second metallization in respect to a direction perpendicular to the at least one line of the first metallization.
7. The substrate according to claim 1 , wherein the at least two gate metallization areas are each separated from the second metallization by a gap with a width in the range from 0.5 mm to 2.0 mm.
8. The substrate according to claim 1 , wherein one gate metallization area is provided as gate peninsula, which is surrounded on the substrate by the second metallization and an edge of the substrate.
9. The substrate according to claim 1 , wherein the second metallization is provided in an L-shape and extends through a connection area of the substrate.
10. The substrate according to claim 1 , wherein a resistor is provided on and connected to the gate contact, and the gate metallization areas are bonded to the gate contact via the resistor.
11. A power semiconductor module comprising:
at least one substrate according to claim 1 ,
wherein multiple power transistors are commonly mounted with associated collectors or emitters on the first metallization of the at least one substrate,
wherein other emitters or collectors of the power transistors are connected to the second metallization,
wherein gate pads of the power transistors are connected to the third metallization, and
the gate contact and the at least two gate metallization areas are interconnected by way of bonding means.
12. The power semiconductor module according to claim 11 ,
wherein multiple power transistors are commonly mounted with their collectors or emitters on the second metallization,
wherein other emitters or collectors of the power transistors are connected to the fourth metallization,
wherein gate pads of the power transistors are connected to the fifth metallization, and
wherein the gate contact and the at least two gate metallization areas are interconnected by way of bonding means.
13. The substrate according to claim 1 , wherein the at least two gate metallization areas of the third metallization are directly interconnectable through bonding means.
14. The substrate according to claim 1 , wherein the at least two gate metallization areas of the fifth metallization are directly interconnectable through the bonding means.