Method of making a gate structure

1. A method of making a gate structure, the method comprising:

forming a gate electrode in an opening defined by a gate dielectric layer having a top surface, wherein forming the gate electrode comprises:

filling a width of a bottom portion of the opening with a first metal material having a first resistance;

defining a recess in the first metal material; and

filling an entire width of a top portion of the opening and the recess with a homogeneous second metal material having a second resistance less than the first resistance, wherein a maximum width of the homogeneous second metal material is equal to a maximum width of the first metal material, and the top surface of the gate dielectric layer is co-planar with a top surface of the homogeneous second metal material.

2. The method of claim 1 , wherein filling the width of the bottom portion of the opening with the first metal material comprises depositing the first metal material over the gate dielectric, and the deposited first metal material includes a gap located within the opening.

3. The method of claim 2 , wherein defining the recess comprises depositing a sacrificial layer over the first metal material, wherein a portion of the sacrificial layer fills the gap.

4. The method of claim 3 , wherein defining the recess further comprises planarizing the first metal material and the sacrificial layer.

5. The method of claim 4 , wherein defining the recess further comprises etching the first metal material to partially expose the portion of the sacrificial layer.

6. The method of claim 5 , wherein defining the recess further comprises removing the portion of the sacrificial layer.

7. The method of claim 6 , wherein removing the portion of the sacrificial layer comprises etching the sacrificial layer using a different etchant from that used for etching the first metal material.

8. The method of claim 1 , wherein filling the entire width of the top portion of the opening and the recess with the homogeneous second metal material comprises:

depositing the homogeneous second metal material over the first metal material and the top surface of the gate dielectric, and

planarizing the homogeneous second metal material.

9. A method of making a transistor, the method comprising:

lining an opening in an insulating layer with a gate dielectric, wherein the gate dielectric defines a trench;

depositing a first metal material into the trench, wherein the first metal material fills a bottom portion of the trench, the first metal material has a first resistance, and depositing the first metal material defines a first recess;

depositing a barrier layer over the first metal material, wherein depositing the barrier layer comprises partially filling the first recess and defining a second recess; and

filling the second recess and an entire width of the trench above the barrier layer with a homogeneous second metal material and having a second resistance less than the first resistance, wherein a maximum width of the homogeneous second metal material is equal to a maximum width of the barrier layer, and a top surface of the gate dielectric is co-planar with a top surface of the homogeneous second metal material.

10. The method of claim 9 , wherein lining the opening with the gate dielectric comprises forming the gate dielectric over a top surface of the insulating layer.

11. The method of claim 10 , further comprising planarizing the gate dielectric to expose the top surface of the insulating layer after lining the opening with the gate dielectric the first metal material.

12. The method of claim 9 , wherein lining the opening with the gate dielectric comprises forming the gate dielectric in the opening between gate spacers.

13. The method of claim 9 , wherein lining the opening with the gate dielectric comprises forming the gate dielectric in the opening defined by an interlayer dielectric (ILD).

14. The method of claim 9 , further comprising forming the opening in the insulating layer by removing a dummy gate structure.

15. The method of claim 9 , wherein lining the opening with the gate dielectric comprises lining the opening with a high-k dielectric material.

16. The method of claim 9 , wherein filling the recess and the entire width of the trench above the first metal material with the homogeneous second metal material comprises forming the homogeneous second metal material over a top surface of the insulating layer.

17. The method of claim 16 , further comprising planarizing the homogeneous second metal material to expose the top surface of the insulating layer.

18. The method of claim 17 , wherein filling the recess and the entire width of the trench above the first metal material with the homogeneous second metal material comprises depositing the homogeneous second metal material in direct contact with the first metal material.

19. A method of making a transistor, the method comprising:

lining an opening in an insulating layer with a gate dielectric, wherein the gate dielectric defines a trench;

depositing a first metal material into the trench, wherein the first metal material fills a bottom portion of the trench, the first metal material has a first resistance, and depositing the first metal material defines a recess; and

filling the recess and an entire width of the trench above the first metal material with a homogeneous second metal material and having a second resistance less than the first resistance, wherein a maximum width of the homogeneous second metal material is equal to a maximum width of the first metal material, and a top surface of the gate dielectric is co-planar with a top surface of the homogeneous second metal material.

20. The method of claim 19 , further comprising forming an interfacial layer between the gate dielectric and a substrate.