Electrically insulating thermal interface on the discontinuity of an encapsulation structure
Method for manufacturing an electronic semiconductor package, in which method an electronic chip ( 100 ) is coupled to a carrier, the electronic chip is at least partially encapsulated by means of an encapsulation structure having a discontinuity, and the carrier is partially encapsulated, and at least one part of the discontinuity and a volume connected thereto adjoining an exposed surface section of the carrier are covered by an electrically insulating thermal interface structure, which electrically decouples at least one part of the carrier with respect to its surroundings.
1. Electronic semiconductor package, comprising:
an electronic chip;
a carrier coupled to the electronic chip;
an encapsulation structure at least partially encapsulating the electronic chip and partially encapsulating the carrier, wherein the encapsulation structure has a discontinuity; and
an electrically insulating thermal interface structure, which covers at least a part of the discontinuity and a volume connected thereto, which volume adjoins an exposed surface section of the carrier, wherein the thermal interface structure electrically decouples at least a part of the carrier with respect to a surrounding of the carrier,
wherein the discontinuity is an annular discontinuity, which surrounds a surface section of the carrier circumferentially and which extends into the encapsulation structure,
wherein side walls of the encapsulation structure surrounding the discontinuity are inclined by an angle in a range of between 5° and 35° with respect to a vertical extension into the encapsulation structure.
2. Electronic semiconductor package in accordance with claim 1 , wherein the thermal interface structure is in direct contact with the carrier within the discontinuity.
3. Electronic semiconductor package in accordance with claim 1 , wherein the thermal interface structure has a thickness in a range between 20 μm and 500 μm.
4. Electronic semiconductor package in accordance with claim 1 , wherein the thermal interface structure comprises a solid body layer of a matrix with filling particles embedded therein.
5. Electronic semiconductor package in accordance with claim 1 , wherein the thermal interface structure comprises a viscous formless material.
6. Electronic semiconductor package in accordance with claim 1 , wherein the encapsulation structure has multiple discontinuities, which are at least partially covered by the electrically insulating thermal interface structure.
7. Electronic semiconductor package in accordance with claim 1 , wherein the thermal interface structure has a higher thermal conductivity than the encapsulation structure.
8. Electronic arrangement, comprising:
an electronic semiconductor package, comprising:
an electronic chip;
a carrier coupled to the electronic chip;
an encapsulation structure at least partially encapsulating the electronic chip and partially encapsulating the carrier, wherein the encapsulation structure has a discontinuity; and
an electrically insulating thermal interface structure, which covers at least a part of the discontinuity and a volume connected thereto, which volume adjoins an exposed surface section of the carrier, wherein the thermal interface structure electrically decouples at least a part of the carrier with respect to a surrounding of the carrier;
wherein the discontinuity is an annular discontinuity, which surrounds a surface section of the carrier circumferentially and which extends into the encapsulation structure,
wherein side walls of the encapsulation structure surrounding the discontinuity are inclined by an angle in a range of between 5° and 35° with respect to a vertical extension into the encapsulation structure.
a heat dissipation element, which is connected externally to the thermal interface structure to provide a thermal coupling with the carrier.