Method for manufacturing semiconductor device comprising electron trap layer
A semiconductor device in which the threshold is adjusted is provided. In a transistor including a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and an electron trap layer between the gate electrode and the semiconductor, the electron trap layer includes crystallized hafnium oxide. The crystallized hafnium oxide is deposited by a sputtering method using hafnium oxide as a target. When the substrate temperature is Tsub (° C.) and the proportion of oxygen in an atmosphere is P (%) in the sputtering method, P≧45−0.15×Tsub is satisfied. The crystallized hafnium oxide has excellent electron trapping properties. By the trap of an appropriate number of electrons, the threshold of the semiconductor device can be adjusted.
1. A method for manufacturing a semiconductor device comprising an electron trap layer between a first semiconductor and a gate electrode, the method comprising the steps of:
forming the electron trap layer by sputtering hafnium oxide, wherein the electron trap layer is formed so that the electron trap layer includes crystallized hafnium oxide;
forming an electrode so as to be electrically connected to the first semiconductor;
forming a second semiconductor; and
forming a third semiconductor,
wherein the first semiconductor is between the second semiconductor and the third semiconductor,
wherein the third semiconductor is between the first semiconductor and the electron trap layer,
wherein the sputtering of the hafnium oxide is performed so that the following condition is satisfied:
P≧ 45−0.15× T
where T is a substrate temperature in degrees centigrade and P is a proportion of oxygen in an atmosphere in percent, and
wherein 0≦P≦100.
2. The method according to claim 1 , wherein the electron trap layer includes electron trap states.
3. The method according to claim 1 , wherein the crystallized hafnium oxide is monoclinic.
4. The method according to claim 1 , wherein the electrode is either a source electrode or a drain electrode.
5. The method according to claim 1 , wherein the first semiconductor is an oxide semiconductor.
6. The method according to claim 1 , further comprising the steps of:
forming a first insulating layer; and
forming a second insulating layer,
wherein the first insulating layer is between the first semiconductor and the electron trap layer, and
wherein the second insulating layer is between the electron trap layer and the gate electrode.
7. The method according to claim 1 , wherein 200≦T≦350.
8. A method for manufacturing a semiconductor device comprising an electron trap layer between a first semiconductor and a gate electrode, the method comprising the steps of:
forming the electron trap layer by sputtering hafnium oxide, wherein the electron trap layer is formed so that the electron trap layer includes crystallized hafnium oxide;
forming a metal electrode so as to be in direct contact with the first semiconductor;
forming a second semiconductor; and
forming a third semiconductor,
wherein the first semiconductor is between the second semiconductor and the third semiconductor,
wherein the third semiconductor is between the first semiconductor and the electron trap layer,
wherein the sputtering of the hafnium oxide is performed so that the following condition is satisfied:
P≧ 45−0.15× T
where T is a substrate temperature in degrees centigrade and P is a proportion of oxygen in an atmosphere in percent, and
wherein 0≦P≦100.
9. The method according to claim 8 , wherein the electron trap layer includes electron trap states.
10. The method according to claim 8 , wherein the crystallized hafnium oxide is monoclinic.
11. The method according to claim 8 , wherein the metal electrode is either a source electrode or a drain electrode.
12. The method according to claim 8 , wherein the first semiconductor is an oxide semiconductor.
13. The method according to claim 8 , further comprising the steps of:
forming a first insulating layer; and
forming a second insulating layer,
wherein the first insulating layer is between the first semiconductor and the electron trap layer, and
wherein the second insulating layer is between the electron trap layer and the gate electrode.
14. The method according to claim 8 , wherein 200≦T≦350.