Memory devices with improved refreshing operation
A method and a system for memory cell programming and erasing with refreshing operation are disclosed. The system includes a selecting module, a processing module and a refresh module. In the method, at first, a target memory cell from a plurality of memory cells in a memory device is selected. Thereafter, the target memory cell belonging to a line of the matrix is programmed or erased by applying a selecting voltage on the target memory cell and a location-related memory cell belonging to the line of the matrix. Then, a refreshing operation to refresh the location-related cell is performed
1. A method, comprising:
selecting a target memory cell from a plurality of memory cells of a matrix in a memory device;
programming or erasing the target memory cell belonging to a line of the matrix by applying a selecting voltage to the target memory cell and a location-related memory cell belonging to the line of the matrix; and
performing a refreshing operation to refresh the location-related memory cell, wherein the refreshing operation comprises:
reading data stored in the location-related memory cell;
writing the data back to the location-related memory cell;
determining if a voltage level of the location-related memory cell is lower than a predetermined verifying voltage level, or if a current level of the location-related memory cell is lower than a predetermined verifying current level; and
rewriting the data back to the location-related memory cell, when the voltage level of the location-related memory cell is higher than or equal to the predetermined verifying voltage level or the current level of the location-related memory cell is lower than the predetermined verifying current level.
2. The method of claim 1 , further comprising initializing an operation count.
3. The method of claim 2 , further comprising:
increasing the operation count when the voltage level of the location-related memory cell is lower than the predetermined verifying voltage level; and
determining if all of the memory cells are checked in accordance with the operation count.
4. The method of claim 2 , further comprising:
increasing the operation count when the current level of the location-related memory cell is lower than the predetermined verifying current level; and
determining if all of the memory cells are checked in accordance with the operation count.
5. The method of claim 1 , wherein the data is a logic data “0” or “1”.
6. A method, comprising:
selecting a target memory cell from a plurality of memory cells of a matrix in a memory device;
programming or erasing the target memory cell belonging to a line of the matrix by applying a selecting voltage to the target memory cell and a location-related memory cell belonging to the line of the matrix; and
performing a refreshing operation to refresh the location-related memory cell, wherein the refreshing operation comprises:
reading data stored in the location-related memory cell;
writing the data back to the location-related memory cell;
determining if a voltage level of the location-related memory cell is higher than a predetermined verifying voltage level, or if a current level of the location-related memory cell is higher than a predetermined verifying current level; and
rewriting the data back to the location-related memory cell, when the voltage level of the location-related memory cell is lower than or equal to the predetermined verifying voltage level or the current level of the location-related memory cell is lower than or equal to the predetermined verifying current level.
7. The method of claim 6 , further comprising initializing an operation count.
8. The method of claim 7 , further comprising:
increasing the operation count when the voltage level of the location-related memory cell is higher than a predetermined verifying voltage level; and
determining if all of the memory cells are checked in accordance with the operation count.
9. The method of claim 7 , further comprising:
increasing the operation count when the current level of the location-related memory cell is higher than the predetermined verifying current level; and
determining if all of the memory cells are checked in accordance with the operation count.
10. The method of claim 6 , wherein the data is a logic data “0” or “1”.
11. A system, comprising:
a selecting module configured to select a target memory cell from a plurality of memory cells arrange in a matrix in a memory device;
a processing module configured to program or erase the target memory cell belonging to a line of the matrix, the operation for programming or erasing the target memory cell including applying a selecting voltage to the target memory cell and a location-related memory cell belonging to the line of the matrix; and
a refresh module configured to perform a refreshing operation on the location-related memory cell, the refreshing operation comprising:
reading data stored in the location-related memory cell;
writing the data back to the location-related memory cell;
determining if a voltage level of the location-related memory cell is lower than a predetermined verifying voltage level, or if a current level of the location-related memory cell is lower than a predetermined verifying current level; and
rewriting the data back to the location-related memory cell, when the voltage level of the location-related memory cell is higher than or equal to the predetermined verifying voltage level or the current level of the location-related memory cell is lower than the predetermined verifying current level.
12. The system of claim 11 , wherein the plurality of memory cells are located at respective intersections of a plurality of bit lines and a plurality of word lines.
13. The system of claim 12 , wherein the plurality of memory cells in the line are electrically connected through one of the plurality of word lines of the memory device.
14. The system of claim 12 , wherein the plurality of memory cells in the line are electrically connected through one of the plurality of bit lines of the memory device.
15. The system of claim 11 , wherein the data is a logic data “0” or “1”.
16. A system, comprising:
a selecting module configured to select a target memory cell from a plurality of memory cells arrange in a matrix in a memory device;
a processing module configured to program or erase the target memory cell belonging to a line of the matrix, the operation for programming or erasing the target memory cell including applying a selecting voltage to the target memory cell and a location-related memory cell belonging to the line of the matrix; and
a refresh module configured to perform a refreshing operation on the location-related memory cell, the refreshing operation comprising:
reading data stored in the location-related memory cell;
writing the data back to the location-related memory cell;
determining if a voltage level of the location-related memory cell is higher than a predetermined verifying voltage level, or if a current level of the location-related memory cell is higher than a predetermined verifying current level; and
rewriting the data back to the location-related memory cell when the voltage level of the location-related memory cell is lower than or equal to the predetermined verifying voltage level or the current level of the location-related memory cell is lower than or equal to the predetermined verifying current level.
17. The system of claim 16 , wherein the plurality of memory cells are located at respective intersections of a plurality of bit lines and a plurality of word lines.
18. The system of claim 17 , wherein the plurality of memory cells in the line are electrically connected through one of the plurality of word lines of the memory device.
19. The system of claim 17 , wherein the plurality of memory cells in the line are electrically connected through one of the plurality of bit lines of the memory device.
20. The system of claim 16 , wherein the data is a logic data “0” or “1”.