Leakage compensation circuit for phase-locked loop (PLL) large thin oxide capacitors
Certain aspects of the present disclosure provide methods and apparatus for compensating, or at least adjusting, for capacitor leakage. One example method generally includes determining a leakage voltage corresponding to a leakage current of a capacitor in a filter for a phase-locked loop (PLL), wherein the determining comprises closing a set of switches for discontinuous sampling of the leakage voltage; based on the sampled leakage voltage, generating a sourced current approximately equal to the leakage current; and injecting the sourced current into the capacitor.
1. A method comprising:
determining a leakage voltage based on a leakage current of a capacitor in a filter for a phase-locked loop (PLL), wherein the determining comprises closing a set of switches for discontinuous sampling of the leakage voltage;
based on the determined leakage voltage, generating a sourced current approximately equal to the leakage current; and
injecting the sourced current into the capacitor.
2. The method of claim 1 , wherein the capacitor comprises a thin oxide capacitor.
3. The method of claim 1 , wherein the injecting comprises injecting the sourced current into the capacitor such that a voltage drop across a resistor in series with the capacitor is approximately zero volts.
4. The method of claim 3 , wherein the determined leakage voltage is equal to a voltage potential generated by the leakage current of the capacitor passing through the resistor in series with the capacitor.
5. The method of claim 1 , wherein generating the sourced current comprises controlling a current source with an amplifier based on the determined leakage voltage.
6. The method of claim 5 , wherein the determining comprises closing the set of switches to:
store the leakage voltage across a sampling capacitor; and
short first and second inputs of the amplifier to a common-mode voltage of the filter.
7. The method of claim 6 , wherein the current source comprises a transistor and wherein the controlling comprises closing another set of switches to:
sense the leakage voltage stored across the sampling capacitor with the first and second inputs of the amplifier; and
connect an output of the amplifier with a gate of the transistor.
8. The method of claim 7 , wherein the set of switches is closed if a charge pump of the PLL is inactive and wherein the other set of switches is closed if the charge pump of the PLL is active.
9. The method of claim 7 , wherein another capacitor is connected between a source and a gate of the transistor and is configured to maintain a gate-to-source voltage of the transistor if the other set of switches is open.
10. The method of claim 6 , wherein the capacitor comprises a thin oxide capacitor and wherein the sampling capacitor comprises a thick oxide capacitor.
11. The method of claim 5 , wherein the determining comprises:
buffering the leakage voltage with a voltage follower; and
closing the set of switches to store the buffered leakage voltage across a sampling capacitor and across another capacitor having a leakage current proportional to the leakage current of the capacitor in the filter.
12. The method of claim 11 , wherein:
the current source comprises a first transistor;
the other capacitor is the same capacitor type as the capacitor in the filter;
a first input of the amplifier is coupled to the other capacitor and to a drain of a second transistor;
a second input of the amplifier is coupled to the sampling capacitor;
an output of the amplifier is coupled to a gate of the second transistor; and
a capacitance ratio of the capacitor to the other capacitor is equal to a size ratio of the first transistor to the second transistor.
13. The method of claim 12 , wherein the controlling comprises:
closing another set of switches to connect the output of the amplifier with a gate of the first transistor; and
driving the gate of the first transistor and the gate of the second transistor with the amplifier.
14. The method of claim 13 , wherein the determining further comprises opening the other set of switches to disconnect the output of the amplifier from the gate of the first transistor and wherein the controlling further comprises opening the set of switches to disconnect an output of the voltage follower from the other capacitor and from the sampling capacitor.
15. The method of claim 13 , wherein the set of switches is closed if a charge pump of the PLL is inactive and wherein the other set of switches is closed if the charge pump is active.
16. The method of claim 11 , wherein the capacitor and the other capacitor comprise thin oxide capacitors and wherein the sampling capacitor comprises a thick oxide capacitor.
17. A circuit comprising:
a filter for a phase-locked loop (PLL) comprising a capacitor;
a set of switches configured to be closed for the circuit to sample a leakage voltage based on a leakage current of the capacitor;
a current source configured to generate a sourced current for injection into the capacitor; and
an amplifier configured to control the current source based on the sampled leakage voltage such that the sourced current is approximately equal to the leakage current.
18. The circuit of claim 17 , wherein the sourced current is injected into the capacitor such that a voltage drop across a resistor in series with the capacitor is approximately zero volts.
19. The circuit of claim 18 , further comprising a charge pump for the PLL, wherein:
a first end of the capacitor is coupled to a reference node for the filter;
a second end of the capacitor is coupled to a first end of the resistor and to the current source; and
a second end of the resistor is coupled to the charge pump.
20. The circuit of claim 17 , further comprising a sampling capacitor, wherein the set of switches is configured to be closed for the circuit to:
store the leakage voltage across the sampling capacitor; and
short first and second inputs of the amplifier to a common-mode voltage of the filter.
21. The circuit of claim 20 , further comprising another set of switches, wherein the current source comprises a transistor and wherein the other set of switches is configured to be closed for the circuit to:
sense the leakage voltage stored across the sampling capacitor with the first and second inputs of the amplifier; and
connect an output of the amplifier with a gate of the transistor.
22. The circuit of claim 21 , further comprising a charge pump for the PLL, wherein the set of switches is closed if the charge pump is inactive and wherein the other set of switches is closed if the charge pump is active.
23. The circuit of claim 21 , further comprising another capacitor connected between a source and a gate of the transistor and configured to maintain a gate-to-source voltage of the transistor if the other set of switches is open.
24. The circuit of claim 20 , wherein the capacitor comprises a thin oxide capacitor and wherein the sampling capacitor comprises a thick oxide capacitor.
25. The circuit of claim 17 , further comprising:
another capacitor having a leakage current proportional to the leakage current of the capacitor in the filter, wherein the other capacitor is coupled to a first input of the amplifier;
a sampling capacitor coupled to a second input of the amplifier; and
a voltage follower configured to buffer the leakage voltage, wherein the set of switches is configured to be closed for the circuit to store the buffered leakage voltage across the other capacitor and across the sampling capacitor.
26. The circuit of claim 25 , wherein:
the current source comprises a first transistor;
the other capacitor is the same capacitor type as the capacitor in the filter;
the first input of the amplifier is coupled to the other capacitor and to a drain of a second transistor;
an output of the amplifier is coupled to a gate of the second transistor; and
a capacitance ratio of the capacitor in the filter to the other capacitor is equal to a size ratio of the first transistor to the second transistor.
27. The circuit of claim 26 , further comprising another set of switches configured, if closed, to connect the output of the amplifier with a gate of the first transistor.
28. The circuit of claim 27 , wherein the other set of switches is configured, if opened, to disconnect the output of the amplifier from the gate of the first transistor and wherein the set of switches is configured, if opened, to disconnect an output of the voltage follower from the other capacitor and from the sampling capacitor.
29. The circuit of claim 27 , further comprising a charge pump for the PLL, wherein the set of switches is closed if the charge pump is inactive and wherein the other set of switches is closed if the charge pump is active.
30. The circuit of claim 25 , wherein the capacitor in the filter and the other capacitor comprise thin oxide capacitors and wherein the sampling capacitor comprises a thick oxide capacitor.