Receiver with clock recovery circuit and adaptive sample and equalizer timing
A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.
1. A receiver comprising:
a data input port;
an edge sampler coupled to the data input port;
clock recovery circuitry having a clock-recovery input port, coupled to the data input port via the edge sampler, and a clock-recovery output port;
a data sampler having a data-sampler input terminal, coupled to the data input port, and a data-sampler output terminal;
an equalizer coupled to the data-sampler input terminal, the equalizer having an equalizer clock terminal; and
an adaptive phase-offset controller coupled between the clock-recovery output port of the clock recovery circuitry and the equalizer clock terminal, the phase-offset controller having a phase-offset control port.
2. The receiver of claim 1 , wherein the data input port is to receive a signal comprised of a series of data symbols and the data sampler is to sample the data symbols to produce a series of sampled data, the receiver further comprising a signal quality measurement circuit, coupled to the phase-offset control port, to derive a quality measure for the sampled data.
3. The receiver of claim 2 , further comprising equalization control circuitry coupled to the signal quality measurement circuit.
4. The receiver of claim 1 , further comprising a second data sampler coupled between the data input port and the clock recovery circuitry.
5. The receiver of claim 4 , wherein the edge sampler receives an edge clock signal having an edge-clock phase, the second data sampler receives a reference-data clock signal having a reference-data phase, and the phase-offset controller issues an equalizer clock signal having an equalizer clock phase.
6. The receiver of claim 5 , wherein the phase-offset controller varies the equalizer clock phase with respect to at least one of the edge-clock phase and the reference-data phase.
7. The receiver of claim 1 , wherein the data sampler includes a data-clock terminal coupled to the equalizer clock terminal.
8. The receiver of claim 1 , wherein the data input port is to receive a signal comprised of a series of data symbols and the data sampler is to sample the data symbols to produce a series of sampled data, the receiver further comprising a signal quality measurement circuit, coupled to the phase-offset control port, to derive a quality measure for the sampled data, and wherein the quality measure includes a measure of intersymbol interference (ISI).
9. The receiver of claim 8 , wherein the equalizer does not equalize based on the measure of ISI.
10. A method comprising:
receiving an analog input signal expressing a series of data symbols;
sampling edges of the series of data symbols to recover an edge timing reference signal from the series of data symbols;
deriving a second timing reference signal from the edge timing reference signal;
applying an equalization signal timed to the second timing reference signal to equalize the input signal;
measuring signal quality of the input signal; and
phase adjusting the second timing reference signal relative to the edge timing reference signal based on the quality of the input signal.
11. The method of claim 10 , wherein measuring the signal quality of the input signal comprises considering a bit-error rate of the series of data symbols.
12. The method of claim 10 , wherein measuring the signal quality of the input signal comprises measuring precursor intersymbol interference (ISI) for the data symbols.
13. The method of claim 10 , wherein measuring the signal quality of the input signal comprises measuring intersymbol interference (ISI) for the data symbols.
14. The method of claim 13 , wherein the ISI is unequalized ISI.
15. An integrated circuit comprising:
a data sampler having a data-sampler input port, to receive an input signal, the data sampler to sample the input signal and provide a series of sampled data symbols on a data sampler output port;
a decision feedback equalizer (DFE) coupled between the data-sampler input port and the data sampler output port, the decision feedback equalizer including an equalizer control port and an equalizer clock port;
an edge sampler to derive edge samples from the input signal;
clock recovery circuitry to recover an edge clock from the edge samples; and
an adaptive phase offset control circuit to provide a DFE clock to the equalizer clock port, wherein the adaptive phase offset circuit varies the phase of the DFE clock relative to the edge clock based on a measure of signal quality for the input signal.
16. The integrated circuit of claim 15 , further comprising timing calibration circuitry to provide the measure of signal quality to the phase offset control circuit.
17. The integrated circuit of claim 15 , further comprising a second data sampler to sample the input signal and to provide the resulting second series of data symbols to the clock recovery circuitry.
18. The integrated circuit of claim 15 , further comprising equalizer control circuitry coupled to the equalizer control port.
19. The integrated circuit of claim 18 , wherein the equalizer control circuitry provides the measure of signal quality.
20. The integrated circuit of claim 15 , wherein the measure of signal quality is based upon a measure of intersymbol interference.