Semiconductor device having a patterned metal layer embedded in an interlayer dielectric layer

1. A semiconductor device, comprising:

a substrate;

a first metal gate on the substrate;

a first hard mask on the first metal gate;

an interlayer dielectric (ILD) layer on top of and around the first metal gate;

a patterned metal layer embedded in the ILD layer, wherein the top surface of the patterned metal layer is lower than the top surface of the first hard mask; and

a patterned dielectric stack on the patterned metal layer, wherein a top surface of the patterned dielectric stack is lower than a top surface of the first hard mask.

2. The semiconductor device of claim 1 , wherein the patterned dielectric stack comprises silicon nitride and silicon dioxide.

3. The semiconductor device of claim 1 , wherein the patterned metal layer comprises TiN.

4. The semiconductor device of claim 1 , further comprising a first contact plug in the ILD layer and electrically connected to a source/drain region adjacent to the first metal gate.

5. The semiconductor device of claim 1 , further comprising a second contact plug in the ILD layer and electrically connected to the patterned metal layer.

6. The semiconductor device of claim 1 , further comprising:

a second metal gate on the substrate and adjacent to the first metal gate; and

a second hard mask on the second metal gate.

7. The semiconductor device of claim 6 , further comprising a third contact plug in the ILD layer and electrically connected to the second metal gate.

8. The semiconductor device of claim 1 , further comprising a shallow trench isolation (STI) in the substrate and directly under the patterned metal layer.