Semiconductor arrangement with electrostatic discharge (ESD) protection
One or more semiconductor arrangements having a stacked configuration and electrostatic discharge (ESD) protection are provided. The semiconductor arrangements include a first substrate, a second substrate, an ESD pad, an ESD device and a first interlayer via connecting the first substrate and the second substrate. The first substrate includes a first PMOS device and a first device and the second substrate includes a first NMOS device and a second device. Alternatively, the first substrate includes a first PMOS device and a first NMOS device and the second substrate includes a first device and a second device.
1. A semiconductor arrangement comprising:
a first substrate comprising:
a first PMOS device comprising a first source/drain region coupled to a first power supply supplying a first voltage; and
a first NMOS device comprising a first source/drain region coupled to a second power supply supplying a second voltage different than the first voltage;
a second substrate comprising:
a first device coupled to a second source/drain region of the first PMOS device; and
a second device coupled to a second source/drain region of the first NMOS device;
an electrostatic discharge (ESD) pad coupled between the first device and the second device, wherein there is no current path between the ESD pad and a gate of the first PMOS device or a gate of the first NMOS device; and
a first interlayer via coupling the first substrate and the second substrate.
2. The semiconductor arrangement of claim 1 , wherein the first interlayer via couples the first PMOS device to the first device.
3. The semiconductor arrangement of claim 1 , wherein at least one of the first device or the second device is at least one of a second PMOS device, a second NMOS device, a first resistor or a second resistor.
4. The semiconductor arrangement of claim 1 , wherein the first device is a second PMOS device and the second device is a second NMOS device.
5. The semiconductor arrangement of claim 1 , wherein the first device is a first resistor and the second device is a second resistor.
6. The semiconductor arrangement of claim 1 , the first power supply corresponding to a positive voltage power supply and the second power supply corresponding to at least one of a negative voltage power supply or ground.
7. The semiconductor arrangement of claim 1 , comprising:
an ESD device coupled to the ESD pad.
8. The semiconductor arrangement of claim 1 , wherein the first substrate and the second substrate are in a stacked configuration.
9. A semiconductor arrangement comprising:
a first substrate comprising:
a first PMOS device comprising a first source/drain region coupled to a first power supply supplying a first voltage; and
a first device coupled to a second source/drain region of the first PMOS device;
a second substrate comprising:
a first NMOS device comprising a first source/drain region coupled to a second power supply supplying a second voltage different than the first voltage; and
a second device coupled to a second source/drain region of the first NMOS device;
an electrostatic discharge (ESD) pad coupled between the first device and the second device, wherein there is no current path between the ESD pad and a gate of the first PMOS device or a gate of the first NMOS device; and
a first interlayer via coupling the first substrate and the second substrate.
10. The semiconductor arrangement of claim 9 , wherein the first interlayer via couples the first device to the second device.
11. The semiconductor arrangement of claim 9 , wherein at least one of the first device or the second device is at least one of a second PMOS device, a second NMOS device, a first resistor or a second resistor.
12. The semiconductor arrangement of claim 9 , wherein the first device is a second PMOS device and the second device is a second NMOS device.
13. The semiconductor arrangement of claim 9 , wherein the first device is a first resistor and the second device is a second resistor.
14. The semiconductor arrangement of claim 9 , the first power supply corresponding to a positive voltage power supply and the second power supply corresponding to at least one of a negative voltage power supply or ground.
15. The semiconductor arrangement of claim 9 , comprising:
an ESD device coupled to the ESD pad.
16. The semiconductor arrangement of claim 9 , wherein the first substrate and the second substrate are in a stacked configuration.
17. A semiconductor arrangement comprising:
a first substrate comprising:
a first PMOS device, comprising:
a first source/drain region coupled to a first power supply supplying a first voltage; and
a second source/drain region; and
a first NMOS device, comprising:
a first source/drain region coupled to a second power supply supplying a second voltage different than the first voltage; and
a second source/drain region;
a second substrate comprising:
a first resistor having a first terminal coupled to the second source/drain region of the first PMOS device; and
a second resistor having a first terminal coupled to the second source/drain region of the first NMOS device; and
an electrostatic discharge (ESD) pad coupled to a second terminal of the first resistor and a second terminal of the second resistor.
18. The semiconductor arrangement of claim 17 , wherein there is no current path between the ESD pad and a gate of the first PMOS device or a gate of the first NMOS device.
19. The semiconductor arrangement of claim 17 , wherein there is no current path between the ESD pad and a gate of the first PMOS device and there is no current path between the ESD pad and a gate of the first NMOS device.
20. The semiconductor arrangement of claim 17 , wherein the first substrate and the second substrate are in a stacked configuration.