System and processor for implementing interruptible batches of instructions
A system, method, and computer program product are provided for scheduling interruptible hatches of instructions for execution by one or more functional units of a processor. The method includes the steps of receiving a batch of instructions that includes a plurality of instructions and dispatching at least one instruction from the batch of instructions to one or more functional units for execution. The method further includes the step of receiving an interrupt request that causes an interrupt routine to be dispatched to the one or more functional units prior to all instructions in the batch of instructions being dispatched to the one or more functional units. When the interrupt request is received, the method further includes the step of storing batch-level resources in a memory to resume execution of the batch of instructions once the interrupt routine has finished execution.
1. A method comprising:
receiving a batch of instructions that includes a plurality of instructions;
dispatching, by a scheduler unit, at least one instruction from the batch of instructions to one or more functional units for execution;
receiving an interrupt request, at the scheduler unit, that causes the scheduler unit to dispatch an interrupt routine to the one or more functional units prior to all instructions in the batch of instructions being dispatched to the one or more functional units, wherein the interrupt routine includes one or more additional instructions that are not included in the batch of instructions, and wherein the scheduler unit is configured to prioritize the dispatching of the one or more additional instructions included in the interrupt routine over the plurality of instructions in the batch of instructions; and
storing batch-level resources in a memory to resume execution of the batch of instructions once the interrupt routine has finished execution.
2. The method of claim 1 , wherein the batch-level resources are stored in a portion of a register file allocated to the batch of instructions.
3. The method of claim 2 , wherein the portion of the register file is allocated to the batch of instructions by the scheduler unit prior to dispatching the at least one instruction from the batch of instructions to one or more functional units for execution.
4. The method of claim 1 , further comprising allocating a portion of a register file for storing the batch-level resources in response to receiving the interrupt request.
5. The method of claim 1 , further comprising:
receiving a second batch of instructions; and
dispatching, by the scheduler unit, at least one instruction from the second batch of instructions to the one or more functional units for execution.
6. The method of claim 5 , wherein the at least one instruction from the second batch of instructions is dispatched prior to dispatching every instruction in the batch of instructions to the functional units for execution.
7. The method of claim 6 , wherein the scheduler unit is configured to arbitrate between the batch of instructions and the second batch of instructions to select an instruction to issue to the one or more functional units.
8. The method of claim 1 , wherein the batch of instructions is associated with a thread block and an instruction from the batch of instructions is dispatched to a number of functional units in parallel during a single clock cycle.
9. The method of claim 1 , wherein the batch-level resources are stored in a cache unit at a memory location allocated to the batch of instructions in response to receiving the interrupt request.
10. A non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform steps comprising:
receiving a batch of instructions that includes a plurality of instructions;
dispatching, by a scheduler unit, at least one instruction from the batch of instructions to one or more functional units for execution;
receiving an interrupt request, at the scheduler unit, that causes the scheduler unit to dispatch an interrupt routine to the one or more functional units prior to all instructions in the batch of instructions being dispatched to the one or more functional units, wherein the interrupt routine includes one or more additional instructions that are not included in the batch of instructions, and wherein the scheduler unit is configured to prioritize the dispatching of the one or more additional instructions included in the interrupt routine over the plurality of instructions in the batch of instructions; and
storing batch-level resources in a memory to resume execution of the batch of instructions once the interrupt routine has finished execution.
11. The non-transitory computer-readable storage medium of claim 10 , wherein the batch-level resources are stored in a portion of a register file allocated to the batch of instructions, and wherein the portion of the register file is allocated to the batch of instructions by the scheduler unit prior to dispatching the at least one instruction from the batch of instructions to one or more functional units for execution.
12. The non-transitory computer-readable storage medium of claim 10 , further comprising:
receiving a second batch of instructions; and
dispatching, by the scheduler unit, at least one instruction from the second batch of instructions to the one or more functional units for execution.
13. The non-transitory computer-readable storage medium of claim 12 , wherein the at least one instruction from the second batch of instructions is dispatched prior to dispatching every instruction in the batch of instructions to the functional units for execution.
14. A system comprising:
one or more functional units configured to execute instructions; and
a scheduler unit configured to:
receive a batch of instructions that includes a plurality of instructions,
dispatch at least one instruction from the batch of instructions to the one or more functional units for execution,
receive an interrupt request that causes the scheduler unit to dispatch an interrupt routine to the one or more functional units prior to all instructions in the batch of instructions being dispatched to the one or more functional units, wherein the interrupt routine includes one or more additional instructions that are not included in the batch of instructions, and wherein the scheduler unit is configured to prioritize the dispatching of the one or more additional instructions included in the interrupt routine over the plurality of instructions in the batch of instructions, and
cause batch-level resources to be stored in a memory to resume execution of the batch of instructions once the interrupt routine has finished execution.
15. The system of claim 14 , wherein the memory is a register file, and the scheduler unit is further configured to store the batch-level resources in a portion of the register file allocated to the batch of instructions.
16. The system of claim 15 , wherein the portion of the register file is allocated to the batch of instructions by the scheduler unit prior to dispatching the at least one instruction from the batch of instructions to one or more functional units for execution.
17. The system of claim 14 , wherein the scheduler unit is further configured to:
receive a second batch of instructions; and
dispatch at least one instruction from the second batch of instructions to the one or more functional units for execution.
18. The system of claim 17 , wherein the at least one instruction from the second batch of instructions is dispatched prior to dispatching every instruction in the batch of instructions to the functional units for execution.
19. The system of claim 14 , wherein the one or more functional units and the scheduler unit are included in a graphics processing unit (GPU).
20. The system of claim 14 , wherein the scheduler unit is further configured to allocate a portion of a register file for storing the batch-level resources in response to receiving the interrupt request.