Method for manufacturing semiconductor device with tensile stress
View Patent ↗A semiconductor device, and a method for manufacturing the same, comprises a source/drain region formed using a solid phase epitaxy (SPE) process to provide partially isolated source/drain transistors. Amorphous semiconductor material at the source/drain region is crystallized and then shrunk through annealing, to apply tensile stress in the channel direction.
1. A method of manufacturing a semiconductor device, comprising, in the following order:
first, etching a semiconductor substrate to form one or more recesses around a channel region, wherein the one or more recesses have a defined depth from a surface of the semiconductor substrate to the bottom of the one or more recesses;
second, forming a continuous isolation layer on a bottom surface and a side surface of the one or more recesses, wherein a portion of the side surface of the channel region adjacent to the surface of the semiconductor substrate is free of said isolation layer so as to provide said recess with an exposed substrate side wall portion;
third, completely filling the one or more recesses having the isolation layer on the bottom surface and the side surface thereof, with a layer of an amorphous semiconductor material using a single deposition step, in which the layer of the amorphous semiconductor material overlies and contacts said isolation layer on the bottom surface and the side surface of the one or more recesses, such that the layer of the amorphous semiconductor material has a top surface aligned with the surface of the semiconductor substrate and in contact with the exposed substrate side wall portion;
fourth, annealing the amorphous semiconductor material to form a source/drain region in contact with the exposed substrate side wall portion, such that tensile stress is applied to the semiconductor device in direction of the channel; and
wherein the forming of the isolation layer further comprises:
forming an oxide layer on the surface of the recess using oxidation; and
etching the oxide layer to expose the portion of the side surface of the channel region adjacent to the surface of the semiconductor substrate.
2. The method of claim 1 , further comprising:
before forming the recess, forming a gate insulating film on the surface of the semiconductor substrate and forming a gate electrode on the gate insulating film.
3. The method of claim 1 , wherein filling the recess with an amorphous semiconductor material comprising:
depositing an amorphous semiconductor material on the semiconductor substrate; and
selectively removing the amorphous semiconductor material such that only the amorphous semiconductor material in the recess remains.
4. The method of claim 3 , wherein selectively removing the amorphous semiconductor material comprises:
planarizing the deposited amorphous semiconductor material; and
etching back the amorphous semiconductor material.
5. The method of claim 4 , wherein the planarizing comprises chemical mechanical polishing.
6. The method of claim 1 , wherein the amorphous semiconductor material comprises amorphous Si.
7. The method of claim 1 , wherein the amorphous semiconductor material comprises amorphous SiC.
8. The method of claim 7 , wherein the amorphous SiC contains 1-4 volume % carbon.
9. The method of claim 1 , wherein the annealing is performed in a N 2 or He atmosphere at 600-750° C. for 2-36 hours.
10. The method of claim 1 , wherein the annealing is performed in a N 2 or He atmosphere at 650° C. for 24 hours.
11. The method of claim 1 , wherein before filling the one or more recesses with the amorphous semiconductor material the semiconductor substrate is subjected to a plasma surface treatment.
12. The method of claim 11 , wherein the plasma surface treatment is a hydrogen plasma treatment performed with an Rf power of 200 W under a pressure of 2 Torrs at room temperature for 1-3 mins.
13. The method of claim 1 , wherein before filling the one or more recesses with the amorphous semiconductor material, a surface annealing treatment is performed on the semiconductor substrate.
14. The method of claim 13 , wherein the surface annealing treatment is hydrogen annealing performed in H 2 atmosphere with a flow rate of 20-200 SLM, under a pressure of 30-760 Torrs and at a temperature of 800° C. for 1-3 mins.
15. The method of claim 1 , wherein the semiconductor device is an nMOS transistor.
16. The method of claim 1 , wherein the semiconductor substrate is a Si substrate, and the isolation layer is a layer of silicon oxide, silicon nitride, silicon oxynitride or silicon nitride oxide.