Synchronizing timestamp counters
A technique includes writing a first count value associated with a first timestamp counter to a first memory local to the first timestamp counter. The technique includes writing a second count value associated with a second timestamp counter to a second memory local to the second timestamp counter. The timestamp counters are synchronized based at least in part on the first and second count values.
1. A method comprising:
writing a first count value associated with a first timestamp counter of a first processor to a first memory local to the first timestamp counter and to the first processor, the first timestamp counter being associated with a first memory controller;
writing a second count value associated with a second timestamp counter of a second processor to a second memory local to the second timestamp counter and to the second processor, the second timestamp counter being associated with a second memory controller other than the first memory controller, the second memory remote to the first timestamp counter and to the first processor, the first memory remote to the second timestamp counter and to the second processor; and
synchronizing the first and second timestamp counters based at least in part on the first and second count values that have been written to the first and second memories, respectively, by at least the first and second timestamp counters exchanging the first and second count values with each other.
2. The method of claim 1 , wherein synchronizing the counters comprises synchronizing the counters to synchronize execution of threads.
3. The method of claim 2 , further comprising executing the first thread on a first processor associated with a first processor socket and executing the second thread on a second processor associated with a second processor socket.
4. The method of claim 1 , wherein writing the first count value comprises storing the first count value in a cache line.
5. The method of claim 1 , wherein writing the first count value comprises storing the first count value inside a first processor package and writing the second count value comprises storing the second count value inside a second processor package other than the first processor package.
6. The method of claim 1 , wherein writing the first and second count values comprises writing the first and second count values to memory locations of a non-uniform memory architecture (NUMA)-based computer.
7. The method of claim 1 , wherein synchronizing the counters comprises synchronizing counters associated with measuring a timing of events occurring in a computer.
8. An apparatus comprising:
a first logical processing core to write a first count value associated with a first timestamp counter of the first logical processing core to a first memory local to the first timestamp counter and to the first logical processing core; and
a second logical processing core other than the first logical processing core to write a second count value associated with a second timestamp counter of the second logical processing core to a second memory local to the second timestamp counter and to the second logical processing core,
wherein the first and second logical processing cores are adapted to synchronize the timestamp counters based at least in part on the first and second count values that have been written to the first and second memories, respectively, by at least the first and second timestamp counters exchanging the first and second count values with each other.
9. The apparatus of claim 8 , wherein the first logical processing core is associated with a memory controller local to the first memory and the second logical processing core is associated with another memory controller, the another memory controller being local to the second memory.
10. The apparatus of claim 8 , wherein the first logical processing core is adapted to read the second count value from the second memory.
11. The apparatus of claim 8 , wherein the first logical processing core is associated with a first processor socket and the second processor is associated with a second processor socket other than the first processor socket.
12. The apparatus of claim 8 , wherein the first and timestamp counters are used for at least one of measuring a timing of events in a computer and synchronizing thread execution in the computer.
13. An article comprising a non-transitory computer readable storage medium to store instructions that when executed by a computer cause the computer to:
write a first count value associated with a first timestamp counter of a first processor to a first memory local to the first timestamp counter and to the first processor, the first timestamp counter being associated with a first memory controller;
write a second count value associated with a second timestamp counter of a second processor to a second memory local to the second timestamp counter and to the second processor, the second timestamp counter being associated with a second memory controller other than the first memory controller, the second memory remote to the first timestamp counter and to the first processor, the first memory remote to the second timestamp counter and to the second processor; and
synchronize the first and second timestamp counters based at least in part on the first and second count values that have been written to the first and second memories, respectively, by at least the first and second timestamp counters exchanging the first and second count values with each other.
14. The article of claim 13 , the storage medium storing instructions that when executed by the computer cause the computer to write the first count value to the first memory and read the second count value from the second memory.
15. The article of claim 13 , the storage medium storing instructions that when executed by the computer cause the computer to synchronize the counters in connection with at least one of synchronizing the measuring of an event timing in the computer and synchronizing the execution of threads in the computer.