At least one general-purpose server is connected to a PE module via Ethernet (trademark). A control unit of the PE module controls a PE circuit and multiple fail memory in a real-time manner, temporarily stores fail information stored in the multiple fail memory, performs data processing on the fail information, and transfers the fail information thus processed to the general-purpose server. Each general-purpose server is controlled according to a computer program so as to perform redundancy analysis for a DUT based on the data received from the PE module.
1. A test system comprising:
a pin electronics module; and
at least one general-purpose server each connected to the pin electronics module via Ethernet,
wherein the pin electronics module comprises:
a pin electronics circuit that acquires fail information with respect to a device under test;
a plurality of fail memories that store the fail information; and
a control unit that controls the pin electronics circuit and the plurality of fail memories in a real-time manner, that temporarily holds the fail information with respect to the plurality of fail memories, that performs data processing on the fail information, and that transfers the processed fail information to the general-purpose server,
and wherein the general-purpose server is controlled according to a computer program so as to perform redundancy analysis for the device under test based on the processed fail information received from the pin electronics module.
2. The test system according to claim 1 , wherein the general-purpose server is configured as a blade server.
3. The test system according to claim 1 , wherein the control unit comprises:
a memory that temporarily stores the fail information; and
a first processor that processes the fail information stored in the memory, and supplies the processed fail information to the general-purpose server via Ethernet.
4. The test system according to claim 3 , wherein the control unit further comprises a second processor that transfers the fail information from the plurality of fail memories to the memory.
5. The test system according to claim 4 , wherein the second processor comprises a programmable logic device.
6. The test system according to claim 1 , configured to allow the number of general-purpose servers to be changed according to a scale of the pin electronics module.
7. The test system according to claim 1 , wherein the at least one general-purpose server each comprise a plurality of cores,
and wherein the plurality of cores are dynamically assigned to the plurality of fail memories.
8. The test system according to claim 1 , wherein the at least one general-purpose server each comprise a plurality of cores,
and wherein after one of the plurality of cores has completed a given operation, said one of the plurality of cores takes over a part of the processing assigned to a different core.
9. The test system according to claim 1 , wherein the at least one general-purpose server each comprise a plurality of resources of the plurality resources,
and wherein while a resource of the plurality resources analyzes one fail pattern by means of one algorithm, another vacant resource analyzes said one fail pattern by means of another algorithm in parallel.
10. A test system comprising:
a pin electronics module; and
at least one blade server each connected to the pin electronics module via Ethernet, wherein the pin electronics module is configured as a hardware device so as to have:
(i) a function of acquiring fail information with respect to a device under test;
(ii) a function of controlling acquisition of the fail information in a real-time manner; and
(iii) a function of transferring the fail information to the blade server,
and wherein the blade server is controlled according to a computer program so as to perform redundancy analysis for the device under test based on the processed fail information received from the pin electronics module.
11. A test apparatus, wherein the test apparatus is connected to at least one general-purpose server via Ethernet in use, and the test apparatus comprises a plurality of pin electronics modules, wherein the pin electronics modules each comprise:
a pin electronics circuit that acquires fail information with respect to a device under test;
a plurality of fail memories that store the fail information; and
a control unit that controls the pin electronics circuit in a real-time manner, that temporarily holds the fail information stored in the plurality of fail memories, that performs data processing on the fail information, and that transfers the processed fail information to the general-purpose server.