Anti-fuse type one-time programmable memory cell array with plurality of unit cells, each made of a metal-oxide-semiconductor (MOS) transistor structure without a selection transistor and method of operation the same

1. An anti-fuse type one-time programmable (OTP) memory cell array including a plurality of unit cells which are respectively located at cross points of a plurality of rows and a plurality of columns, the anti-fuse type OTP memory cell array comprising:

a plurality of well regions respectively disposed in the plurality of rows, wherein each of the well regions is shared by the unit cells in the same row;

a plurality of anti-fuse gates respectively disposed in the plurality of columns to intersect the plurality of well regions;

a plurality of source/drain regions respectively disposed in portions of the well regions between the plurality of anti-fuse gates; and

a plurality of drain regions respectively disposed in the well regions located at one side of a last anti-fuse gate disposed in a last column, which is opposite to a first anti-fuse gate disposed in a first column,

wherein each of the unit cells includes one anti-fuse transistor having a metal-oxide-semiconductor (MOS) transistor structure without a selection transistor.

2. The anti-fuse type OTP memory cell array of claim 1 , wherein a conductivity type of the plurality of well regions is opposite to a conductivity type of the plurality of source/drain regions and the plurality of drain regions.

3. The anti-fuse type OTP memory cell array of claim 2 ,

wherein the plurality of well regions are P-type; and

wherein the plurality of source/drain regions and the plurality of drain regions are N-type.

4. The anti-fuse type OTP memory cell array of claim 2 , further comprising:

a deep well region that surrounds sidewalls and bottom surfaces of the plurality of well regions.

5. The anti-fuse type OTP memory cell array of claim 4 , wherein a conductivity type of the deep well region is opposite to the conductivity type of the plurality of well regions.

6. The anti-fuse type OTP memory cell array of claim 1 ,

wherein each of the anti-fuse transistors disposed in the first column has a half MOS transistor structure; and

wherein the first anti-fuse gate disposed in the first column includes a first sidewall which is vertically aligned with one sidewalls of the source/drain regions between the first anti-fuse gate and a second anti-fuse gate disposed in a second column, and a second sidewall which is located over the well regions.

7. The anti-fuse type OTP memory cell array of claim 1 , further comprising:

a plurality of word lines electrically connected to the plurality of anti-fuse gates, respectively;

a plurality of well bias lines electrically connected to the plurality of well regions, respectively; and

a plurality of bit lines electrically connected to the plurality of drain regions, respectively.

8. The anti-fuse type OTP memory cell array of claim 1 , further comprising:

a plurality of channel regions disposed in upper regions of the well regions overlapping with the anti-fuse gates.

9. The anti-fuse type OTP memory cell array of claim 1 , wherein each of the source/drain regions has two opposite sidewalls that partially overlap with two adjacent anti-fuse gates, and each of the drain regions has a sidewall that partially overlaps with the anti-fuse gate adjacent thereto.

10. An anti-fuse type one-time programmable (OTP) memory cell array comprising:

a plurality of unit cells respectively located at cross points of a plurality of rows and a plurality of columns, each of the unit cells including an anti-fuse transistor having a metal-oxide-semiconductor (MOS) transistor structure;

a plurality of word lines respectively disposed in the plurality of columns, the anti-fuse transistors arrayed in each column sharing any one of the plurality of word lines;

a plurality of well bias lines respectively disposed in the plurality of rows, the anti-fuse transistors arrayed in each row sharing any one of the plurality of well bias lines;

a plurality of bit lines respectively connected to drain terminals of the anti-fuse transistors arrayed in a last column of the plurality of columns; and

a plurality of PN diodes provided between drain terminals of the anti-fuse transistors and the well bias lines,

wherein the anti-fuse transistors arrayed in each row are connected in series.

11. The anti-fuse type OTP memory cell array of claim 10 , wherein anodes of the PN diodes are connected to the well bias lines and cathodes of the PN diodes are connected to the drain terminals of the anti-fuse transistors.

12. The anti-fuse type OTP memory cell array of claim 11 , further comprising:

a deep well bias line; and

a plurality of deep well PN diodes coupled between the deep well bias line and the well bias lines.

13. The anti-fuse type OTP memory cell array of claim 12 , wherein anodes of the deep well PN diodes are connected to the well bias lines and cathodes of the deep well PN diodes are connected to the deep well bias line.

14. The anti-fuse type OTP memory cell array of claim 10 , wherein all source terminals of the anti-fuse transistors arrayed in a first column of the plurality of columns electrically float.

15. An anti-fuse type one-time programmable (OTP) memory cell array comprising:

a plurality of unit cells respectively located at cross points of a plurality of rows and a plurality of columns, each of the unit cells including an anti-fuse transistor having a metal-oxide-semiconductor (MOS) transistor structure;

a plurality of word lines respectively connected to the anti-fuse transistors;

a well bias line which is shared by the anti-fuse transistors;

a plurality of bit lines respectively connected to drain terminals of the anti-fuse transistors arrayed in a last column of the plurality of columns; and

a plurality of PN diodes provided between drain terminals of the anti-fuse transistors and the well bias line.

16. The anti-fuse type OTP memory cell array of claim 15 , wherein the anti-fuse transistors arrayed in each row are connected in series.