Methods of forming under device interconnect structures
Methods of forming microelectronic interconnect under device structures are described. Those methods and structures may include forming a device layer in a first substrate, forming at least one routing layer in a second substrate, and then coupling the first substrate with the second substrate, wherein the first substrate is bonded to the second substrate.
1. A method of forming a structure comprising:
forming at least one routing layer in a first substrate having a first bonding layer comprising a first semiconductor material wherein the first substrate does not include a device layer;
forming a device layer in a second substrate having a second bonding layer comprising a second semiconductor material; and
coupling the first substrate with the second substrate, wherein the first semiconductor material of the first substrate is bonded to the second semiconductor material of the second substrate.
2. The method of claim 1 further comprising wherein the routing layer comprises at least one of a power, a ground or signal routing layer.
3. The method of claim 1 further comprising wherein the at least one routing layer comprises one of a Vcc, a Vss, and an I/O delivery structure.
4. The method of claim 1 further comprising wherein the first substrate and second substrate are layer transferred and bonded to one another.
5. The method of claim 4 further comprising wherein a first bonding layer disposed on the first substrate and a second bonding layer disposed on the second substrate are directly bonded together.
6. The method of claim 1 further comprising wherein the second substrate comprises substantially all power and I/O conductive interconnects, and wherein one of a Vss and a Vcc are coupled to the at least one routing layer disposed in the first substrate.
7. The method of claim 1 further comprising wherein the second substrate comprises substantially all power and I/O bumps, and wherein both Vss and Vcc are coupled to the routing layers in the first substrate.
8. The method of claim 7 further comprising wherein a mimcap is formed in the first substrate.
9. The method of claim 1 further comprising wherein the second substrate comprises I/O and Vcc bumps, and wherein Vss is coupled to the at least one routing layer in the first substrate, wherein Vss is delivered by bumps that contact a grounded heat sink.
10. The method of claim 1 further comprising wherein the second substrate comprises I/O and Vss bumps, and wherein Vcc is coupled to the at least one routing layer disposed in the first substrate, wherein Vcc is delivered by bumps that contact a grounded heat sink.
11. The method of claim 1 further comprising wherein the second substrate comprises an I/O bump, and wherein Vcc and Vss are coupled to the at least one routing layer disposed in the first substrate, wherein power is delivered by bumps on the second substrate.
12. The method of claim 1 further comprising wherein the first substrate comprises bumps delivering I/O, Vss and Vcc, and wherein no signals are delivered on the second substrate.
13. The method of claim 12 further comprising wherein a heat sink is coupled to the first substrate.
14. The method of claim 1 wherein the first substrate comprises at least one wider signal routing line for long distance wiring resource and lower RC than routing lines of the second substrate.
15. The method of claim 1 wherein the second substrate comprises a smaller thickness than a thickness of the first substrate.
16. The method of claim 1 wherein the second substrate comprises a single crystal silicon substrate.
17. The method of claim 1 wherein the routing lines of the second substrate are thinner than the routing lines of the first substrate, and wherein the thickness of the routing lines disposed in the first substrate provide power delivery.
18. The method of claim 1 wherein the structure comprises a device, and wherein a package substrate is coupled to the device.
19. The method of claim 18 wherein a heat sink is coupled to one of the first and the second substrate.
20. A method of forming a package structure comprising:
forming a first bonding layer comprising a first semiconductor material on a first substrate, wherein the first substrate comprises at least one routing layer and does not include a device layer;
forming a second bonding layer comprising a second semiconductor material on a device layer of a second substrate; and
bonding the first bonding layer with the second bonding layer.
21. The method of claim 20 further comprising wherein a donor portion of the second substrate is cleaved from the second substrate.
22. The method of claim 20 further comprising wherein circuit elements are formed in the device layer subsequent to bonding the first bonding layer to the second bonding layer.
23. The method of claim 20 further comprising wherein the first substrate is bonded to the second substrate by using a layer transfer process.
24. The method of claim 20 further comprising wherein the first substrate comprise no greater than one layer of metal routing lines.
25. The method of claim 20 further comprising wherein the first bonding layer and the second bonding layer comprise silicon.
26. A structure comprising:
at least one routing layer disposed in a first substrate, wherein the first substrate does not include a device layer;
a device layer disposed in a second substrate; and
a bonding layer coupling the first substrate with the second substrate wherein the bonding layer comprises a first semiconductor material bonded to a second semiconductor material.
27. The structure of claim 26 further comprising wherein the at least one routing layer comprises at least one of a power, a ground or a signal routing layer.
28. The structure of claim 26 further comprising wherein the at least one routing layer is conductively coupled to one of Vcc, Vss and I/O disposed in the device layer.
29. The structure of claim 26 further comprising wherein the device layer comprises a different substrate material than a material of the first substrate.
30. The structure of claim 26 further comprising wherein a first bonding layer disposed on the first substrate and a second bonding layer disposed on the second substrate are directly bonded together.
31. The structure of claim 26 further comprising wherein the second substrate comprises substantially all power and I/O conductive interconnects, and wherein one of Vss and Vcc are conductively coupled to routing layers disposed in the first substrate.
32. The structure of claim 26 further comprising wherein the second substrate comprises substantially all power and I/O conductive interconnects, and wherein both Vss and Vcc are conductively coupled to routing layers disposed in the first substrate.
33. The structure of claim 32 further comprising wherein a mimcap is disposed in the first substrate.
34. The structure of claim 26 further comprising wherein the second substrate comprises I/O and Vcc, and wherein Vss is conductively coupled to routing layers disposed in the first substrate, wherein Vss is delivered by bumps that contact a grounded heat sink.
35. The structure of claim 26 further comprising wherein the second substrate comprises I/O and Vss, and wherein Vcc is conductively coupled to routing layers disposed in the first substrate, wherein Vcc is delivered by bumps that contact a grounded heat sink.
36. The structure of claim 26 further comprising wherein the second substrate comprises I/O, and wherein Vcc and Vss are conductively coupled to routing layers disposed in the first substrate, wherein power is delivered by bumps on the first substrate.
37. The structure of claim 26 further comprising wherein the first substrate comprises bumps capable of delivering I/O, Vss and Vcc, and wherein the second substrate comprises no signal lines.
38. The method of claim 37 further comprising wherein the second substrate comprises a heat sink.
39. The method of claim 26 wherein the first substrate comprises at least one wider signal routing line for long distance wiring and lower RC.
40. The structure of claim 26 wherein the second substrate comprises a thickness that is less than a thickness of the first substrate.
41. The structure of claim 26 wherein the second substrate comprises a single crystal silicon substrate.
42. The structure of claim 26 wherein the routing lines of the second substrate are thinner than the routing lines of the first substrate, and wherein the routing lines disposed in the first substrate are capable of providing power delivery.
43. The structure of claim 26 wherein the structure comprises a device, and wherein a package substrate is coupled to the device.
44. The structure of claim 43 further comprising wherein the package substrate comprises a BBUL package substrate.
45. The structure of claim 26 wherein a heat sink is coupled to one of the first or second substrate.
46. The structure of claim 26 further comprising wherein the first substrate comprise no greater than one layer of metal routing lines.
47. The structure of claim 26 further comprising wherein the first bonding layer and the second bonding layer comprise silicon.
48. The structure of claim 26 wherein the device layer further comprises at least one of a CPU die and a memory die.
49. The structure of claim 26 further comprising a system comprising:
a bus communicatively coupled to the structure; and
an eDRAM communicatively coupled to the bus.
50. The structure of claim 26 further comprising wherein the structure comprises a monolithic 3D device.