Code design and high-throughput decoder architecture for layered decoding of a low-density parity-check code
A low-density parity-check (LDPC) decoder may receive LDPC coded data. The LDPC decoder may perform a decoding iteration associated with decoding the LDPC coded data. The decoding iteration may be performed by processing a group of layers. Each layer may include a corresponding set of check node elements, and may be processed by causing each check node element, of the set of check node elements corresponding to the layer, to update a set of variable node elements, connected to the check node element and associated with the LDPC coded data, based on a check node function associated with the check node element. The decoding iteration may be performed such that each layer is processed in parallel, and such that each check node element updates the corresponding set of variable node elements in parallel. The LDPC decoder may provide a result of performing the decoding iteration.
1. A computing device, comprising:
one or more processors configured to:
receive information that identifies a design threshold associated with a low-density parity-check (LDPC) code;
determine information associated with a permutation matrix for the LDPC code,
the permutation matrix including a group of rows,
each row, of the group of rows, corresponding to a check node element of a group of check node elements associated with the LDPC code,
the permutation matrix including a group of columns,
each column, of the group of columns, corresponding to a variable node element of a group of variable node elements associated with the LDPC code, and
the permutation matrix including a set of values,
each value, of the set of values, corresponding to a particular check node element, of the group of check node elements, and a particular variable node element of the group of variable node elements, and
each value, of the set of values, identifying a connection between the particular check node element and the particular variable node element;
compute a parallelization factor associated with the permutation matrix,
the parallelization factor being computed based on the set of values included in the permutation matrix;
determine, based on the parallelization factor, whether the permutation matrix satisfies the design threshold; and
provide information indicating whether the permutation matrix satisfies the design threshold,
where the one or more processors, when computing the parallelization factor, are configured to:
determine a group of column differences associated with the permutation matrix,
each column difference, of the group of column differences, corresponding to a column of the group of columns, and being equal to a smallest difference between any two values included in the column; and
identify the parallelization factor based on the group of column differences,
the parallelization factor being equal to a smallest value included in the group of column differences.
2. A computing device, comprising:
one or more processors configured to:
receive information that identifies a design threshold associated with a low-density parity-check (LDPC) code;
determine information associated with a permutation matrix for the LDPC code,
the permutation matrix including a group of rows,
each row, of the group of rows, corresponding to a check node element of a group of check node elements associated with the LDPC code,
the permutation matrix including a group of columns,
each column, of the group of columns, corresponding to a variable node element of a group of variable node elements associated with the LDPC code, and
the permutation matrix including a set of values,
each value, of the set of values, corresponding to a particular check node element, of the group of check node elements, and a particular variable node element of the group of variable node elements, and
each value, of the set of values, identifying a connection between the particular check node element and the particular variable node element;
compute a parallelization factor associated with the permutation matrix,
the parallelization factor being computed based on the set of values included in the permutation matrix;
determine, based on the parallelization factor, whether the permutation matrix satisfies the design threshold; and
provide information indicating whether the permutation matrix satisfies the design threshold,
where the one or more processors are further configured to:
determine, based on the parallelization factor, a maximum performance metric achievable for the LDPC code;
compare the maximum performance metric to the design threshold; and
where the one or more processors, when determining whether the permutation matrix satisfies the design threshold, are further to:
determine whether the permutation matrix satisfies the design threshold based on comparing the maximum performance metric to the design threshold.
3. A computing device, comprising:
one or more processors configured to:
receive information that identifies a design threshold associated with a low-density parity-check (LDPC) code;
determine information associated with a permutation matrix for the LDPC code,
the permutation matrix including a group of rows,
each row, of the group of rows, corresponding to a check node element of a group of check node elements associated with the LDPC code,
the permutation matrix including a group of columns,
each column, of the group of columns, corresponding to a variable node element of a group of variable node elements associated with the LDPC code, and
the permutation matrix including a set of values,
each value, of the set of values, corresponding to a particular check node element, of the group of check node elements, and a particular variable node element of the group of variable node elements, and
each value, of the set of values, identifying a connection between the particular check node element and the particular variable node element;
compute a parallelization factor associated with the permutation matrix,
the parallelization factor being computed based on the set of values included in the permutation matrix;
determine, based on the parallelization factor, whether the permutation matrix satisfies the design threshold; and
provide information indicating whether the permutation matrix satisfies the design threshold,
where the one or more processors are further configured to:
divide the permutation matrix into a first sub-matrix and a second sub-matrix,
the first sub-matrix including a first sub-group of rows, of the group of rows, the group of columns, and a first sub-set of values of the set of values,
the second sub-matrix including a second sub-group of rows, of the group of rows, the group of columns, and a second sub-set of values of the set of values;
compute, based on the first sub-set of values, a first parallelization factor associated with the first sub-matrix;
compute, based on the second sub-set of values, a second parallelization factor associated with the second sub-matrix; and
determine, based on the first parallelization factor and the second parallelization factor, whether the permutation matrix satisfies the design threshold.
4. A computing device, comprising:
one or more processors configured to:
receive information that identifies a design threshold associated with a low-density parity-check (LDPC) code;
determine information associated with a permutation matrix for the LDPC code,
the permutation matrix including a group of rows,
each row, of the group of rows, corresponding to a check node element of a group of check node elements associated with the LDPC code,
the permutation matrix including a group of columns,
each column, of the group of columns, corresponding to a variable node element of a group of variable node elements associated with the LDPC code, and
the permutation matrix including a set of values,
each value, of the set of values, corresponding to a particular check node element, of the group of check node elements, and a particular variable node element of the group of variable node elements, and
each value, of the set of values, identifying a connection between the particular check node element and the particular variable node element;
compute a parallelization factor associated with the permutation matrix,
the parallelization factor being computed based on the set of values included in the permutation matrix;
determine, based on the parallelization factor, whether the permutation
matrix satisfies the design threshold; and
provide information indicating whether the permutation matrix satisfies the design threshold, where the one or more processors are further configured to:
determine, based on the parallelization factor, that an LDPC decoder, associated with decoding data coded using the LDPC code, cannot implement a fully parallel layered decoder architecture to decode the data coded using the LDPC code; and
where the one or more processors, when determining whether the permutation matrix satisfies the design threshold, are further configured to:
determine whether the permutation matrix satisfies the design threshold based on determining that the LDPC decoder cannot implement the fully parallel layered decoder architecture.
5. The computing device of claim 4 , where the one or more processors are further configured to:
determine, after determining that the LDPC decoder cannot implement the fully parallel layered decoding architecture, that the LDPC decoder can implement a partially parallel layered decoder architecture to decode the data coded using the LDPC code; and
where the one or more processors, when determining whether the permutation matrix satisfies the design threshold, are further configured to:
determine whether the permutation matrix satisfies the design threshold based on determining that the LDPC decoder can implement the partially parallel layered decoder architecture.
6. The computing device of claim 4 , where the one or more processors are further configured to:
determine, after determining that the LDPC decoder cannot implement the fully parallel layered decoding architecture, that the LDPC decoder can implement a modified fully parallel layered decoder architecture to decode the data coded using the LDPC code; and
where the one or more processors, when determining whether the permutation matrix satisfies the design threshold, are further configured to:
determine whether the permutation matrix satisfies the design threshold based on determining that the LDPC decoder can implement the modified fully parallel layered decoder architecture.
7. A method, comprising:
determining, by a device, information that identifies a design threshold associated with a low-density parity-check (LDPC) code;
receiving, by the device, information associated with a permutation matrix associated with designing the LDPC code,
the permutation matrix including a group of rows,
each row, of the group of rows, corresponding to a processing element of a group of processing elements associated with the LDPC code,
the permutation matrix including a group of columns,
each column, of the group of columns, corresponding to a storage element of a group of storage elements associated with the LDPC code, and
the permutation matrix including a set of values,
each value, of the set of values, corresponding to a particular processing element, of the group of processing elements, and a particular storage element of the group of storage elements, and
each value, of the set of values, identifying a connection between the particular processing element and the particular storage element;
determining, by the device, a parallelization factor associated with the permutation matrix,
the parallelization factor being computed based on the set of values included in the permutation matrix;
identifying, by the device and based on the parallelization factor, whether the permutation matrix satisfies the design threshold; and
providing, by the device, information indicating whether the permutation matrix satisfies the design threshold,
where determining the parallelization factor comprises:
determining a group of column differences associated with the permutation matrix,
each column difference, of the group of column differences, corresponding to a column of the group of columns, and being equal to a smallest difference between any two values included in the column; and
identifying the parallelization factor based on the group of column differences,
the parallelization factor being equal to a smallest value included in the group of column differences.
8. A method, comprising:
determining, by a device, information that identifies a design threshold associated with a low-density parity-check (LDPC) code;
receiving, by the device, information associated with a permutation matrix associated with designing the LDPC code,
the permutation matrix including a group of rows,
each row, of the group of rows, corresponding to a processing element of a group of processing elements associated with the LDPC code,
the permutation matrix including a group of columns,
each column, of the group of columns, corresponding to a storage element of a group of storage elements associated with the LDPC code, and
the permutation matrix including a set of values,
each value, of the set of values, corresponding to a particular processing element, of the group of processing elements, and a particular storage element of the group of storage elements, and
each value, of the set of values, identifying a connection between the particular processing element and the particular storage element;
determining, by the device, a parallelization factor associated with the permutation matrix,
the parallelization factor being computed based on the set of values included in the permutation matrix;
identifying, by the device and based on the parallelization factor, whether the permutation matrix satisfies the design threshold;
providing, by the device, information indicating whether the permutation matrix satisfies the design threshold;
determining, based on the parallelization factor, a maximum performance metric achievable for the LDPC code;
comparing the maximum performance metric to the design threshold; and
where identifying whether the permutation matrix satisfies the design threshold further comprises:
identifying whether the permutation matrix satisfies the design threshold based on comparing the maximum performance metric to the design threshold.
9. A method, comprising:
determining, by a device, information that identifies a design threshold associated with a low-density parity-check (LDPC) code;
receiving, by the device, information associated with a permutation matrix associated with designing the LDPC code,
the permutation matrix including a group of rows,
each row, of the group of rows, corresponding to a processing element of a group of processing elements associated with the LDPC code,
the permutation matrix including a group of columns,
each column, of the group of columns, corresponding to a storage element of a group of storage elements associated with the LDPC code, and
the permutation matrix including a set of values,
each value, of the set of values, corresponding to a particular processing element, of the group of processing elements, and a particular storage element of the group of storage elements, and
each value, of the set of values, identifying a connection between the particular processing element and the particular storage element;
determining, by the device, a parallelization factor associated with the permutation matrix,
the parallelization factor being computed based on the set of values included in the permutation matrix;
identifying, by the device and based on the parallelization factor, whether the permutation matrix satisfies the design threshold;
providing, by the device, information indicating whether the permutation matrix satisfies the design threshold;
dividing the permutation matrix into a first sub-matrix and a second sub-matrix,
the first sub-matrix including a first sub-group of rows, of the group of rows, the group of columns, and a first sub-set of values of the set of values,
the second sub-matrix including a second sub-group of rows, of the group of rows, the group of columns, and a second sub-set of values of the set of values;
determining, based on the first sub-set of values, a first parallelization factor associated with the first sub-matrix;
determining, based on the second sub-set of values, a second parallelization factor associated with the second sub-matrix; and
identifying, based on the first parallelization factor and the second parallelization factor, whether the permutation matrix satisfies the design threshold.
10. A method, comprising:
determining, by a device, information that identifies a design threshold associated with a low-density parity-check (LDPC) code;
receiving, by the device, information associated with a permutation matrix associated with designing the LDPC code,
the permutation matrix including a group of rows,
each row, of the group of rows, corresponding to a processing element of a group of processing elements associated with the LDPC code,
the permutation matrix including a group of columns,
each column, of the group of columns, corresponding to a storage element of a group of storage elements associated with the LDPC code, and
the permutation matrix including a set of values,
each value, of the set of values, corresponding to a particular processing element, of the group of processing elements, and a particular storage element of the group of storage elements, and
each value, of the set of values, identifying a connection between the particular processing element and the particular storage element;
determining, by the device, a parallelization factor associated with the permutation matrix,
the parallelization factor being computed based on the set of values included in the permutation matrix;
identifying, by the device and based on the parallelization factor, whether the permutation matrix satisfies the design threshold;
providing, by the device, information indicating whether the permutation matrix satisfies the design threshold;
determining, after determining the parallelization factor, that an LDPC decoder, associated with decoding data coded using the LDPC code, cannot implement a fully parallel layered decoder architecture to decode the data coded using the LDPC code; and
where identifying whether the permutation matrix satisfies the design threshold further comprises:
identifying whether the permutation matrix satisfies the design threshold based on determining that the LDPC decoder cannot implement the fully parallel layered decoder architecture.
11. The method of claim 10 , further comprising:
determining, after determining that the LDPC decoder cannot implement the fully parallel layered decoding architecture, that the LDPC decoder can implement a modified fully parallel layered decoder architecture to decode the data coded using the LDPC code; and
where identifying whether the permutation matrix satisfies the design threshold further comprises:
identifying whether the permutation matrix satisfies the design threshold based on determining that the LDPC decoder can implement the modified fully parallel layered decoder architecture.