Printed interconnects for semiconductor packages
A method forming a packaged semiconductor device includes providing a first semiconductor die (first die) having bond pads thereon mounted face-up on a package substrate or on a die pad of a lead frame (substrate), wherein the substrate includes terminals or contact pads (substrate pads). A first dielectric layer is formed including printing a first dielectric precursor layer including a first ink having a first liquid carrier solvent extending from the substrate pads to the bond pads. A first interconnect precursor layer is printed including a second ink having a second liquid carrier over the first dielectric layer extending from the substrate pads to the bond pads. Sintering or curing the first interconnect precursor layer removes at least the second liquid carrier to form an electrically conductive interconnect including an ink residue which connects respective substrate pads to respective bond pads.
1. A packaged semiconductor device, comprising:
a first semiconductor die having a plurality of bond pads thereon mounted face up on a substrate having a plurality of substrate pads;
a first dielectric layer comprising a first ink residue extending from said plurality of substrate pads to said plurality of bond pads; and
a first electrically conductive interconnect comprising a second ink residue on said first dielectric layer extending from said respective ones of said plurality of substrate pads to respective ones of said plurality of bond pads to connect said respective ones of said plurality of substrate pads to said respective ones of said plurality of bond pads.
2. The packaged semiconductor device of claim 1 , further comprising:
a second dielectric layer comprising a third ink residue on said first electrically conductive interconnect; and
printing a second electrically conductive interconnect comprising an fourth ink residue over said second dielectric layer to provide a multi-level conductor interconnect which connects said respective ones of said ones of said plurality of substrate pads to said respective ones of said plurality of bond pads.
3. The packaged semiconductor device of claim 2 , wherein said multi-level conductor interconnect comprises a microstrip waveguide.
4. The packaged semiconductor device of claim 2 , wherein said multi-level conductor interconnect comprises a stripline waveguide.
5. The packaged semiconductor device of claim 2 , wherein said multi-level conductor interconnect comprises a slotline waveguide.
6. The packaged semiconductor device of claim 1 , wherein said second ink residue comprises a plurality of metal particles.
7. The packaged semiconductor device of claim 1 , wherein said substrate comprises a package substrate and said package substrate includes an inset region, and wherein said first semiconductor die is within said inset region.
8. The packaged semiconductor device of claim 1 , wherein said first ink residue has a porosity of at least 20% in at least a portion thereof.
9. The packaged semiconductor device of claim 1 , wherein said second ink residue comprises an electrically conductive polymer.
10. The packaged semiconductor device of claim 1 , wherein said substrate comprises a package substrate.
11. The packaged semiconductor device of claim 10 , wherein said package substrate comprises a printed circuit board (PCB).
12. The packaged semiconductor device of claim 10 , wherein said package substrate comprises an organic substrate.
13. The packaged semiconductor device of claim 10 , wherein said package substrate comprises a flexible plastic substrate.
14. The packaged semiconductor device of claim 10 , wherein said package substrate comprises a paper-based substrate.
15. The packaged semiconductor device of claim 1 , wherein said substrate comprises a lead frame having a die pad.
16. The packaged semiconductor device of claim 1 , wherein said substrate pads comprises terminals pads.
17. The packaged semiconductor device of claim 1 , wherein said substrate pads comprises contact pads.
18. The packaged semiconductor device of claim 1 , wherein said second ink residue comprises a doped semiconductor.