Nonvolatile memory device having a gate coupled to resistors
A nonvolatile memory device having a first resistive element coupled between a common node and a bit line; a second resistive element coupled between the common node and a word line; and a pass transistor having a gate coupled to the common node, a first node coupled to a reference voltage, and a second node coupled to an output, wherein the word line is orthogonal to the bit line.
1. A nonvolatile memory device comprising:
a first resistive element coupled between a common node and a bit line;
a second resistive element coupled between the common node and a word line; and
a pass transistor having a gate coupled to the common node, a first node coupled to a reference voltage, and a second node coupled to an output,
wherein:
the word line is orthogonal to the bit line,
the bit line is on a first metal layer,
the first resistive element is coupled between the first metal layer and a second metal layer, wherein the second metal layer is a metal layer that is located higher that the first metal layer, and
the second resistive element is coupled between the second metal layer and a third metal layer, wherein the third metal layer is a metal layer that is located higher than the second metal layer.
2. The nonvolatile memory device of claim 1 , wherein at least one of (i) the first resistive element and (ii) the second resistive element is a variable resistance cell.
3. The nonvolatile memory device of claim 1 , wherein:
the first resistive element and the second resistive element have opposite polarities;
the first resistive element comprises Pt/Ta 2 O 5 /TaOx/Ir; and
the second resistive element comprises Ir/TaOx/Ta 2 O 5 /Pt.
4. The nonvolatile memory device of claim 1 , wherein the first resistive element comprises material that is different from the second resistive element.
5. The nonvolatile memory device of claim 1 , wherein a bit stored in the nonvolatile memory device is not destroyed during a read operation.
6. The nonvolatile memory device of claim 1 , wherein the pass transistor is configured to be scaled linearly with the first and second resistive elements during a scaling operation.
7. The nonvolatile memory device of claim wherein the second resistive element is stacked on top of the first resistive element.
8. The nonvolatile memory device of claim 1 , wherein the first and second resistive elements have a complementary switch configuration.
9. The nonvolatile memory device of claim 1 , wherein the first and second resistive elements are configured to be one SET and the other RESET simultaneously.
10. The nonvolatile memory device of claim 1 , wherein the pass transistor has dimensions that are based on a read current at the output.
11. The nonvolatile memory device of claim 1 , wherein a voltage V GATE at the gate of the pass transistor is based on:
a voltage V WL on the word line;
a voltage V BL on the bit line;
a resistance R 1 of the first resistive element; and
a resistance R 2 of the second resistive element, wherein:
V
GATE
=
(
V
WL
-
V
BL
)
(
R
1
R
1
+
R
2
)
.
12. The nonvolatile memory device of claim 1 , wherein the memory device is configured to store a “1” when the word line is at a first programming voltage and the bit line is at a second programming voltage, and
wherein the first and second programming voltages are of equal magnitude, the first programming voltage is positive and the second programming voltage is negative.
13. The nonvolatile memory device of claim 1 , wherein the memory device is configured to store a “0” when the word line is at a second programming voltage and the bit line is at a first programming voltage, and
wherein the first and second programming voltages are of equal magnitude, the first programming voltage is positive, and the second programming voltage is negative.
14. A field programmable gate array (FPGA) comprising:
a nonvolatile memory device comprising:
a first resistive element coupled between a common node and a bit line;
a second resistive element coupled between the common node and a word line; and
a pass transistor having a gate coupled to the common node, a first node coupled to a reference voltage, and a second node coupled to an output,
wherein:
the word line is orthogonal to the bit line
the bit line is on a first metal layer,
the first resistive element is coupled between the first metal layer and a second metal layer, wherein the second metal layer is a metal layer that is located higher that the first metal layer, and
the second resistive element is coupled between the second metal layer and a third metal layer, wherein the third metal layer is a metal layer that is located higher than the second metal layer.