IP Library Granted Patent US 9,508,667
Granted Patent B2
US 9,508,667 · App. 14/581,825 · Granted Nov 29, 2016

Formation of solder and copper interconnect structures and associated techniques and configurations

Inventor: Edward R. Prack (Phoenix, AZ)
Assignee: Intel Corporation
H01L24/11H01L21/768H01L23/53228H01L2224/1132H01L2224/11318H01L2224/11332H01L2224/11505H01L2224/11849H01L2224/13147H01L2924/14
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Quick Facts
Patent No.
US 9,508,667
App. No.
14/581,825
Granted
Nov 29, 2016
Kind
B2
Abstract

Embodiments of the present disclosure are directed toward formation of solder and copper interconnect structures and associated techniques and configurations. In one embodiment, a method includes providing an integrated circuit (IC) substrate and depositing a solderable material on the IC substrate using an ink deposition process, a binder printing system, or a powder laser sintering system. In another embodiment, a method includes providing an integrated circuit (IC) substrate and depositing a copper powder on the IC substrate using an additive process to form a copper interconnect structure. Other embodiments may be described and/or claimed.

Claims (13)

1. A method comprising:

providing an integrated circuit (IC) substrate;

depositing a solderable ink on the IC substrate using an ink deposition process, wherein the solderable ink includes a solder powder mixed with a no residue flux (NRF) material that includes a base polymer of polyarylene carbonate (PAC) material and a formic acid fluxing agent; and

reflowing the deposited solderable ink to form one or more solder bumps on the IC substrate, wherein a first solder bump of the one or more solder bumps has a size that is different than a size of a second solder bump of the one or more solder bumps.

2. The method of claim 1 , wherein the solderable ink includes a solder powder mixed with a stabilizing binder that is stable at room temperature and configured to decompose at an elevated temperature above the room temperature.

3. The method of claim 1 , wherein:

the IC substrate includes a contact;

providing the IC substrate comprises providing a die, wafer, or package substrate; and

depositing the solderable ink comprises depositing a solderable material on the contact using an ink jet printer according to a computer-aided design (CAD) file.

4. The method of claim 1 , wherein:

the IC substrate includes a contact;

providing the IC substrate comprises providing a die, wafer, or package substrate; and

depositing the solderable ink comprises depositing a solderable material on the contact using an aerosol jet printing system according to a computer-aided design (CAD) file.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 23, 2014
From: PRACK, EDWARD R.
To: INTEL CORPORATION
Reel/Frame 034580/0942 →
Continuity (1)
Related Publication 20160181217A1 · Jun 23, 2016