Thin film transistor substrate and method for manufacturing the same

1. A thin film transistor substrate comprising a matrix of a plurality of pixels, wherein each of said plurality of pixels includes:

a semiconductor film located on a plurality of portions of a substrate;

a thin film transistor that includes at least a gate insulating film and a gate electrode;

said gate insulating film being located on a first portion of said semiconductor film on said substrate and being formed of a first insulating film,

said gate electrode being located on said gate insulating film and being formed of a first conductive film,

a source wiring that is formed of said first conductive film and is formed on laminated films of said semiconductor film and said first insulating film;

a second insulating film covering said thin film transistor and said source wiring;

a source-electrode-portion contact hole and a drain-electrode-portion contact hole that penetrate said second insulating film in a thickness direction and penetrate said gate insulating film in the thickness direction to reach said first portion of said semiconductor film;

a gate-electrode-portion contact hole that penetrates said second insulating film in the thickness direction to reach said gate electrode;

a source-wiring-portion contact hole that penetrates said second insulating film in the thickness direction to reach said source wiring;

a source electrode connected to said semiconductor film through said source-electrode-portion contact hole, said source electrode being formed of a second conductive film;

a source-electrode connecting wiring that extends from said source electrode and is connected to said source wiring through said source-wiring-portion contact hole, said source-electrode connecting wiring being formed of said second conductive film;

a drain electrode connected to said semiconductor film through said drain-electrode-portion contact hole, said drain electrode being formed of said second conductive film;

a gate wiring connected to said gate electrode through said gate-electrode-portion contact hole, said gate wiring being formed of said second conductive film;

a pixel electrode that extends from said drain electrode and covers said second insulating film corresponding to a pixel region defined by said source wiring and said gate wiring, said pixel electrode being formed of said second conductive film;

a third insulating film that covers an upper surface of said substrate including said second insulating film; and

a counter electrode located to be opposed to said pixel electrode via said third insulating film lying therebetween, said counter electrode being formed of a third conductive film,

wherein said counter electrode has a plurality of slits provided across a surface thereof.

2. The thin film transistor substrate according to claim 1 , wherein

a planar pattern of said gate electrode is smaller than a planar pattern of said first portion of said semiconductor film on said substrate,

said source-electrode-portion contact hole and said drain-electrode-portion contact hole are located to sandwich said gate-electrode-portion contact hole therebetween, and

a region of said semiconductor film that is sandwiched between said source electrode and said drain electrode and located below said gate electrode is a channel region.

3. The thin film transistor according to claim 1 , wherein each of said plurality of pixels further includes:

a gate-electrode-portion upper-layer contact hole that penetrates said third insulating film in the thickness direction to reach said gate wiring; and

an upper-layer gate wiring connected to said gate wiring through said gate-electrode-portion upper-layer contact hole, said upper-layer gate wiring being formed of said third conductive film.

4. The thin film transistor substrate according to claim 1 , wherein said thin film transistor substrate includes:

a gate terminal formed on laminated films of said semiconductor film and said first insulating film, said gate terminal being formed of said first conductive film;

a gate-terminal-portion first contact hole that penetrates said second insulating film in the thickness direction to reach said gate terminal;

a gate-terminal extraction electrode connected to said gate terminal through said gate-terminal-portion first contact hole, said gate-terminal extraction electrode being formed of said second conductive film;

a source terminal formed on laminated films of said semiconductor film and said first insulating film, said source terminal being formed of said first conductive film;

a source-terminal-portion first contact hole that penetrates said second insulating film in the thickness direction to reach said source terminal; and

a source-terminal extraction electrode connected to said source terminal through said source-terminal-portion first contact hole, said source-terminal extraction electrode being formed of said second conductive film.

5. The thin film transistor substrate according to claim 4 , wherein said thin film transistor substrate further includes:

a gate-terminal-portion second contact hole that penetrates said third insulating film in the thickness direction to reach said gate-terminal extraction electrode;

a gate terminal pad connected to said gate-terminal extraction electrode through said gate-terminal-portion second contact hole, said gate terminal pad being formed of said third conductive film;

a source-terminal-portion second contact hole that penetrates said third insulating film in the thickness direction to reach said source-terminal extraction electrode; and

a source terminal pad connected to said source-terminal extraction electrode through said source-terminal-portion second contact hole, said source terminal pad being formed of said third conductive film.

6. The thin film transistor substrate according to claim 3 , wherein each of said plurality of pixels further includes an uppermost-layer gate wiring connected to said upper-layer gate wiring, said uppermost-layer gate wiring being formed of a fourth conductive film.

7. The thin film transistor substrate according to claim 1 , wherein each of said plurality of pixels further includes:

a common electrode formed of said semiconductor film that is located on a second portion of said substrate, said first insulating film that is located on said semiconductor film, and said first conductive film that is located on said first insulating film;

a counter-electrode-portion contact hole that penetrates said second and third insulating films on said common electrode in the thickness direction to reach said common electrode; and

an upper-layer common-electrode connecting wiring connected to said common electrode through said counter-electrode-portion contact hole, said upper-layer common-electrode connecting wiring being formed of said third conductive film and being integral with said counter electrode.

8. The thin film transistor substrate according to claim 1 , wherein each of said plurality of pixels further includes:

a common electrode formed of said semiconductor film that is located on a second portion of said substrate, said first insulating film that is located on said semiconductor film, and said first conductive film that is located on said first insulating film;

a common-electrode connection-portion contact hole that penetrates said second insulating film on said common electrode in the thickness direction to reach said common electrode;

a common-electrode connecting wiring connected to said common electrode through said common-electrode connection-portion contact hole, said common-electrode connecting wiring being formed of said second conductive film;

a counter-electrode-portion contact hole that penetrates said third insulating film in the thickness direction to reach said common-electrode connecting wiring; and

an upper-layer common-electrode connecting wiring connected to said common-electrode connecting wiring through said counter-electrode-portion contact hole, said upper-layer common-electrode connecting wiring being formed of said third conductive film and being integral with said counter electrode.

9. The thin film transistor substrate according to claim 1 , wherein each of said plurality of pixels further includes a metal light-shielding film and a fourth insulating film laminated on said substrate in the stated order under said semiconductor film.

10. The thin film transistor substrate according to claim 1 , wherein said semiconductor film is formed of an oxide semiconductor.

11. The thin film transistor substrate according to claim 10 , wherein said oxide semiconductor is formed of an InGaZnO-based oxide semiconductor containing indium oxide, gallium oxide, and zinc oxide.