IP Library › Granted Patent US 9,513,974
Granted Patent B2
US 9,513,974 · App. 14/593,941 · Granted Dec 6, 2016

Task scheduler mechanism, operating system, and multiprocessor system

Inventor: Yoshiyuki Ito (Kawasaki, JP)
Assignee: Renesas Electronics Corporation
G06F9/52
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Quick Facts
Patent No.
US 9,513,974
App. No.
14/593,941
Granted
Dec 6, 2016
Kind
B2
Abstract

In a multiprocessor system having a high-performance processor and a low-power-consumption processor, tasks are properly assigned to the high-performance processor or to the low-power-consumption processor even if the tasks include those commonly used by a plurality of applications. The applications each include a plurality of tasks that are driven by an input or sequentially driven by another task. A task scheduler mechanism includes a synchronization mechanism that causes a driven task to inherit a priority assigned to the input or a synchronizing task, and a task assignment mechanism that determines in accordance with the inherited priority whether to assign the driven task to the high-performance processor or to the low-power-consumption processor.

Claims (37)

1. A task scheduler mechanism executed by a multiprocessor system that is capable of executing a plurality of applications and equipped with a high-performance processor and a low-power-consumption processor, the applications each including a plurality of tasks that are driven by an input or sequentially driven by another task, the task scheduler mechanism comprising:

a synchronization mechanism that causes a driven task to inherit a priority assigned to the input or a synchronizing task; and

a task assignment mechanism that determines, in accordance with the inherited priority, whether to assign the driven task to the high-performance processor or to the low-power-consumption processor,

wherein the synchronization mechanism includes a first management table that stores a priority assigned to each task and stores the synchronizing task in association with the driven task,

wherein, in the first management table, the priority of the driven task is replaced by the priority of the synchronizing task to cause the driven task to inherit the priority assigned to the synchronizing task,

wherein the first management table is capable of storing the association between the synchronizing task and the driven task as well as flag information indicating whether the driven task is capable of parallelly operating on a plurality of contexts,

wherein, when assigning a processor to a driven task, the task assignment mechanism references the flag information,

wherein, if the driven task comprises a task formed of a single context, the task assignment mechanism is capable of exercising control to acquire an operating status of the task, and

wherein, if the task is running, the task assignment mechanism is capable of exercising control to transfer the task from a processor running the task to another processor.

2. The task scheduler mechanism according to claim 1 ,

wherein the applications each includes a sub-process group that includes a plurality of tasks, and

wherein, when the priority of a particular task is to be changed in the first management table, the synchronization mechanism changes the priorities of the other tasks belonging to the same sub-process group as the particular task to a same priority as that of the particular task.

3. The task scheduler mechanism according to claim 1 ,

wherein the task assignment mechanism assigns to the high-performance processor or to the low-power-consumption processor in accordance with the inherited priority and with a power and/or load status of the multiprocessor system.

4. The task scheduler mechanism according to claim 1 ,

wherein the task assignment mechanism includes a second management table that stores a priority of a driven task in association with an assigned processor, and references the second management table to determine, in accordance with a priority inherited by the driven task, whether to assign to the high-performance processor or to the low-power-consumption processor.

5. The task scheduler mechanism according to claim 4 ,

wherein the second management table stores the assigned processor in association with a combination of the priority of a driven task and a power and/or load status of the multiprocessor system, and

wherein the task assignment mechanism references the second management table to assign to the high-performance processor or to the low-power-consumption processor in accordance with the inherited priority and with the power and/or load status of the multiprocessor system.

6. The task scheduler mechanism according to claim 5 ,

wherein the task scheduler mechanism further includes a load status monitoring/report mechanism and a system power supply status monitoring/report mechanism,

wherein the load status monitoring/report mechanism monitors the load status of the multiprocessor system and supplies the monitored load status to the task assignment mechanism, and

wherein the system power supply status monitoring/report mechanism monitors the status of power supply to the multiprocessor system and supplies the monitored power status to the task assignment mechanism.

7. The task scheduler mechanism according to claim 6 ,

wherein the task scheduler mechanism further includes a power saving control mechanism, and

wherein the power saving control mechanism receives the load status supplied from the load status monitoring/report mechanism and the power status supplied from the system power supply status monitoring/report mechanism and controls a power-consumption-related operating status of the high-performance processor and/or the low-power-consumption processor in accordance with the load status and with the power status.

8. An operating system comprising the task scheduler mechanism according to claim 1 .

9. A multiprocessor system comprising the task scheduler mechanism according to claim 1 .

10. A method of task scheduling, as executed by a multiprocessor system that is capable of executing a plurality of applications and equipped with at least one high-performance processor and at least one low-power-consumption processor, the applications each including a plurality of tasks that are driven by an input or sequentially driven by another task, the method comprising:

storing, in a first management table, a priority assigned to each task and synchronizing tasks in association with driven tasks; and

replacing, in the first management table, the priority of the driven task by the priority of the synchronizing task, to cause the driven task to inherit the priority assigned to the synchronizing task;

causing a driven task to inherit a priority assigned to the input or a synchronizing task; and

determining, in accordance with the inherited priority, whether to assign the driven task to the high-performance processor or to the low-power-consumption processor,

wherein the applications each includes a sub-process group that includes a plurality of tasks, and, when the priority of a particular task is to be changed in the first management table, the priorities of the other tasks belonging to the same sub-process group as the particular task are changed to the same priority as that of the particular task,

wherein the first management table is capable of storing the association between the synchronizing task and the driven task as well as flag information indicating whether the driven task is capable of parallelly operating on a plurality of contexts, and, when assigning a processor to a driven task, flag information is referenced,

wherein, if the driven task comprises a task formed of a single context, an operating status of the task can be acquired, and, if the task is running, the task can be transferred from a processor running the task to another processor, and

wherein tasks are assigned to the high-performance processor or to the low-power-consumption processor in accordance with the inherited priority and with the power and/or load status of the multiprocessor system.

Assignments (2)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 12, 2015
From: ITO, YOSHIYUKI
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 034680/0068 →
Priority Claims (1)
JP 2014-008579 · Jan 21, 2014 · national
Continuity (1)
Related Publication 20150205644A1 · Jul 23, 2015