Branch synthetic generation across multiple microarchitecture generations
View Patent ↗Branch sequences for branch prediction performance test are generated by performing the following steps: (i) generating a branch node graph, by a branch node graph generator machine logic set, based, at least in part, upon a set of branch traces of a workload or benchmark code; (ii) generating a first assembly pattern file, for use with a first instruction set architecture (ISA)/microarchitecture set, by an assembly pattern generator machine logic set, based, at least in part, upon the branch node graph so as to mimic the control-flow pattern of the workload or benchmark code; and (iii) running the assembly pattern file on the first ISA/microarchitecture set to obtain first execution results.
1. A method comprising:
generating a branch node graph, by a branch node graph generator machine logic set, based, at least in part, upon a set of branch traces;
generating a first assembly pattern file, for use with a first instruction set architecture (ISA)/microarchitecture set, by an assembly pattern generator machine logic set, based, at least in part, upon the branch node graph;
running the assembly pattern file on the first ISA/microarchitecture set to obtain first execution results; and
generating a second assembly pattern file, for use with a second ISA/microarchitecture set, by an assembly pattern generator machine logic set, based, at least in part, upon the branch node graph;
wherein:
the generation of the first assembly pattern file uses a first application binary interface data set, specific to the first ISA/microarchitecture set, so that the assembly pattern file can run on the first ISA/microarchitecture set; and
the generation of the second assembly pattern file uses a second application binary interface data set, specific to the second ISA/microarchitecture set, so that the assembly pattern file can run on the second ISA/microarchitecture set.
2. The method of claim 1 wherein the first and second ISA/microarchitecture sets have a common ISA and are different in microarchitecture type.
3. The method of claim 2 further comprising:
running the second assembly pattern file on the second ISA/microarchitecture set to obtain second execution results; and
comparing the first execution results with the second execution results.
4. The method of claim 3 wherein the first and second execution results relate to branch prediction performance of the first and second ISA/microarchitecture sets, respectively.
5. A method comprising:
generating a branch node graph, by a branch node graph generator machine logic set, based, at least in part, upon a set of branch traces;
generating a first assembly pattern file, for use with a first instruction set architecture (ISA)/microarchitecture set, by an assembly pattern generator machine logic set, based, at least in part, upon the branch node graph; and
running the assembly pattern file on the first ISA/microarchitecture set to obtain first execution results;
wherein:
the generation of the first assembly pattern file uses data from the following tables: (i) a conditional pattern table, (ii) a static address table, and (iii) a dynamic address table; and
the running of the first assembly pattern file on the first ISA/microarchitecture set uses data from the following tables: (i) the conditional pattern table, (ii) the static address table, and (iii) the dynamic address table.