Power module and method of packaging the same
Provided are a power module having an integrated power semiconductor and a method of packaging the same. The power module according to an aspect of the present invention includes a power semiconductor chip based on silicon and insulating substrates respectively disposed at both surfaces of the power semiconductor chip and including a metal pattern electrically and directly connected to the power semiconductor chip.
1. A power module comprising:
a power semiconductor chip based on silicon;
an upper insulating substrate disposed on an upper surface of the power semiconductor chip;
a pattern formed on a first surface of the upper insulating substrate, the pattern being electrically and directly connected to the power semiconductor chip; and
a dielectric layer formed on a second surface of the upper insulating substrate, the second surface being opposite of the first surface.
2. The power module of claim 1 , further comprising a lower insulating substrate disposed on a lower surface of the power semiconductor chip.
3. The power module of claim 1 , wherein the insulating substrates are directly connected to the power semiconductor chip via solder.
4. The power module of claim 2 , wherein the pattern is a metal wiring pattern.
5. The power module of claim 4 , wherein the upper insulating substrate further comprises:
an inner portion, wherein the pattern is disposed on a surface of the inner portion; and
an outer portion electrically connected to a power device outside of a package.
6. The power module of claim 4 , wherein the pattern is made of any one of copper, copper alloy, nickel plated copper, aluminum, or aluminum alloy.
7. The power module of claim 1 , further comprising:
a heat sink layer configured to cover the second surface; and
a heat sink attached to the heat sink layer via solder.
8. A method of packaging a power module, comprising:
forming a pattern on a first surface of an upper insulating substrate;
disposing a power semiconductor chip based on silicon under the upper insulating substrate;
disposing and bonding a lower insulating substrate under the power semiconductor chip; and
forming a dielectric layer on a second surface of the upper insulating substrate opposite the first surface.
9. The method of claim 8 , wherein the pattern is a metal pattern electrically and directly connected to the power semiconductor chip.
10. The method of claim 9 , wherein the pattern is made of any one of copper, copper alloy, nickel plated copper, aluminum, or aluminum alloy.
11. The method of claim 8 , wherein an outer portion of the upper insulating substrate is electrically connected to a power device outside a package.
12. The method of claim 8 , wherein the insulating substrates and the power semiconductor chip are directly attached via solder.
13. The method of claim 8 , wherein the disposing and bonding the lower insulating substrate further comprises forming a heat sink layer configured to cover the second surface, and attaching a heat sink.
14. A power module comprising:
a power semiconductor chip based on silicon;
an upper insulating substrate disposed on an upper surface of the power semiconductor chip;
a pattern formed on a first surface of the upper insulating substrate, the pattern being electrically and directly connected to the power semiconductor chip;
a dielectric layer formed on a second surface of the upper insulating substrate, the second surface being opposite of the first surface;
a heat sink layer configured to cover the second surface; and
a heat sink attached to the heat sink layer using solder.