Adaptive blanking timer for short circuit detection

1. A gate driver integrated circuit for driving an external n-type MOSFET (NMOS) transistor having a gate, a drain and a source, the drain being coupled through a load to a power supply, the gate driver integrated circuit comprising:

a gate driver output configured to drive the gate of the external NMOS transistor;

a first comparator operable to receive the drain voltage of the external NMOS transistor and compare it to a reference voltage representative of a short circuit condition between the drain and the power supply, the first comparator being configured to output a first value if the drain voltage is greater than the reference voltage and to output a second value if the drain voltage is less than or equal to the reference voltage;

control circuitry configured to receive the output of the first comparator and to pull the voltage of the gate driver output low if the comparator output is of the first value;

adaptive masking circuitry operable, upon an application of an “on” signal to the gate driver output, to mask the output of the first comparator such that a condition of the drain voltage being greater than the reference voltage does not cause the control circuitry to pull the voltage of the gate driver output low, the adaptive masking circuitry being operable to detect a Miller plateau in the gate voltage of the external NMOS transistor, wherein the adaptive masking circuitry is operable to stop masking the output of the first comparator after the end of said Miller plateau.

2. The gate driver integrated circuit of claim 1 , wherein if the adaptive masking circuitry fails to detect a Miller plateau in the gate voltage of the external NMOS transistor, the adaptive masking circuitry is operable to stop masking the comparator output after the gate of the external NMOS transistor becomes fully charged.

3. The gate driver integrated circuit of claim 1 , wherein said masking of the output of the first comparator by the adaptive masking circuitry comprises preventing said first value of the comparator output from being provided to the control circuitry.

4. The gate driver integrated circuit of claim 1 , further comprising a gate driver MOSFET transistor configured to receive an input signal at its gate and to provide a gate driver signal to the gate driver output of the gate driver integrated circuit.

5. The gate driver integrated circuit of claim 4 , wherein the adaptive masking circuitry comprises a second comparator operable to compare the drain voltage and source voltage of the gate driver MOSFET, wherein the second comparator is operable to output a first value if the difference between the drain voltage and source voltage is less than a predetermined threshold value, and to output a second value if the difference between the drain voltage and source voltage is greater than the predetermined threshold value, wherein if the output of the second comparator comprises said second value, the adaptive masking circuitry is operable to prevent the first value of the output of the first comparator from being provided to the control circuitry.

6. The gate driver integrated circuit of claim 5 , wherein said first output value of the first comparator is a logical “1,” said second output value of the first comparator is a logical “0,” said first output value of the second comparator is a logical “1,” and said second output value of the second comparator is a logical “0,” and wherein the adaptive masking circuitry further comprises an AND gate having a first input that receives the output of the first comparator, a second input that receives the output of the second comparator, and an output that is provided to the control circuitry, wherein the control circuitry is operable to pull the voltage of the gate driver output low if the output of the AND gate is a logical “1”.