Integrated circuits with electrical fuses and methods of forming the same

1. A method of forming an integrated circuit, the method comprising:

forming at least one transistor over a substrate, wherein forming the at least one transistor comprises:

forming a gate dielectric structure over a substrate;

forming a work-function metallic layer over the gate dielectric structure;

forming a conductive layer over the work-function metallic layer; and

forming a source/drain (S/D) region being disposed adjacent to each sidewall of the gate dielectric structure;

forming a diffusion barrier layer between the gate dielectric structure and the work-function layer; and

forming at least one electrical fuse over the substrate, wherein forming the at least one electrical fuse comprises:

forming a first semiconductor layer over the substrate; and

forming a first silicide layer on the first semiconductor layer, wherein the diffusion barrier layer is formed subsequent to the first silicide layer.

2. The method of claim 1 , wherein the diffusion barrier is formed around the work-function metallic layer.

3. The method of claim 1 , wherein forming the diffusion barrier, forming the work-function metallic layer and forming the conductive layer comprise:

forming a second semiconductor layer over the gate dielectric structure before forming the first silicide layer;

forming a second silicide layer on the second semiconductor layer;

forming a cap layer covering the first silicide layer and exposing the second silicide layer;

removing the second silicide layer and the second semiconductor layer to form a first opening that is left by the removed second silicide layer and the second semiconductor layer; and

sequentially forming the diffusion barrier, the work-function metallic layer and the conductive layer in the first opening.

4. The method of claim 1 , wherein forming the electrical fuse comprises forming the electrical fuse over a shallow trench isolation (STI) feature in the substrate.

5. The method of claim 4 , wherein forming the gate dielectric layer comprises forming the gate dielectric layer over the STI feature.

6. The method of claim 4 , wherein forming the S/D region comprises forming the S/D region in contact with the STI feature.

7. The method of claim 1 , further comprising protecting the electrical fuse during formation of the diffusion barrier layer.

8. A method of forming an integrated circuit, the method comprising:

forming a first semiconductor layer in a transistor region over a substrate and a second semiconductor layer in a fuse region over the substrate;

forming a first silicide layer on the first semiconductor layer and a second silicide layer on the second semiconductor layer;

forming a dielectric layer around the first and second semiconductor layers, exposing the first and second silicide layers;

forming a cap layer covering the second silicide layer and exposing the first silicide layer;

removing the first silicide layer and the first semiconductor layer to form a first opening that is left by the removed first silicide layer and the removed first semiconductor layer;

sequentially forming a work-function metallic layer and a conductive layer in the first opening; and

forming a diffusion barrier between the substrate and the work-function metallic layer, wherein the diffusion barrier is formed subsequent to the first silicide layer.

9. The method of claim 8 , wherein the diffusion barrier is formed around the work-function metallic layer.

10. The method of claim 8 , further comprising forming an electrical fuse over the substrate.

11. The method of claim 10 , wherein forming the electrical fuse comprises forming the electrical fuse over a shallow trench isolation (STI) feature in the substrate.

12. The method of claim 11 , wherein forming the gate dielectric layer comprises forming the gate dielectric layer over the STI feature.

13. The method of claim 11 , wherein forming the S/D region comprises forming the S/D region in contact with the STI feature.

14. A method of forming an integrated circuit, the method comprising:

forming at least one transistor over a substrate, wherein forming the at least one transistor comprises:

forming a gate dielectric structure over the substrate;

forming a work-function metallic layer over the gate dielectric structure;

forming a conductive layer over the work-function metallic layer, wherein the work-function metallic layer contacts at least one sidewall of the conductive layer; and

forming a source/drain (S/D) region being disposed adjacent to each sidewall of the gate dielectric structure;

forming a diffusion barrier layer over the gate dielectric structure, the diffusion barrier layer positioned between the work-function metallic layer and at least one spacer; and

forming at least one electrical fuse over an isolation structure, the isolation structure formed in the substrate, wherein forming the at least one electrical fuse comprises:

forming a first semiconductor layer over the substrate;

forming a first silicide layer on the first semiconductor layer, wherein the diffusion barrier layer is formed subsequent to the first silicide layer; and

forming a cap layer over the first silicide layer prior to forming the work-function metallic layer.

15. The method of claim 14 , wherein forming the at least one transistor comprises forming at least one spacer over sidewalls of at least one transistor, and

forming the work-function metallic layer comprises forming the work-function metallic layer between the conductive layer and the at least one spacer.

16. The method of claim 14 , wherein forming the at least one transistor further comprises forming a silicide layer over the gate dielectric structure prior to forming the work-function metallic layer over the gate dielectric structure.