Topology specific replicated bus unit addressing in a data processing system
A technique for handling cache-inhibited operations in a data processing system includes receiving, at a replicated bus unit, a cache-inhibited (CI) operation. The replicated bus unit determines whether an address associated with the CI operation matches an address for the replicated bus unit and whether a source indicated by the CI operation is associated with the replicated bus unit. In response to the address associated with the CI operation matching the address for the replicated bus unit and the source indicated by the CI operation being associated with the replicated bus unit, the replicated bus unit processes the CI operation. In response to the address associated with the CI operation not matching the address for the replicated bus unit or the source indicated by the CI operation not being associated with the replicated bus unit, the replicated bus unit ignores the CI operation.
1. A method of handling cache-inhibited operations in a data processing system, comprising:
receiving, at a replicated bus unit, a cache-inhibited (CI) operation;
determining, by the replicated bus unit, whether an address of the CI operation matches an address for the replicated bus unit and whether a source indicated by the CI operation is a source that is serviced by the replicated bus unit;
in response to the address of the CI operation matching the address for the replicated bus unit and the source indicated by the CI operation being a source that is serviced by the replicated bus unit, processing, by the replicated bus unit, the CI operation; and
in response to the address of the CI operation not matching the address for the replicated bus unit or the source indicated by the CI operation not being a source that is serviced by the replicated bus unit, ignoring, by the replicated bus unit, the CI operation.
2. The method of claim 1 , wherein the replicated bus unit is included in a processing cluster.
3. The method of claim 1 , wherein the replicated bus unit is included in a processing node.
4. The method of claim 1 , wherein the replicated bus unit includes a base address register (BAR) that stores the address of the replicated bus unit.
5. The method of claim 1 , wherein the CI operation is a CI load operation or a CI store operation.
6. The method of claim 1 , wherein the replicated bus unit is an interrupt controller.
7. The method of claim 1 , further comprising:
returning, by the replicated bus unit, data to the source indicated by the CI operation.
8. The method of claim 7 , wherein the source corresponds to a master located within a storage subsystem.