IP Library Granted Patent US 9,536,473
Granted Patent B2
US 9,536,473 · App. 15/187,988 · Granted Jan 3, 2017

Display device and a method of manufacturing display device

Inventors: Tetsuo Minami (Tokyo, JP); Yukihito Iida (Kanagawa, JP); Katsuhide Uchino (Kanagawa, JP)
Assignee: Sony Corporation
G09G3/3233G09G3/3266H01L27/3279G09G2300/0426G09G2300/0819G09G2300/0842G09G2300/0861G09G2300/0866G09G2320/0233H01L2227/323
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Quick Facts
Patent No.
US 9,536,473
App. No.
15/187,988
Granted
Jan 3, 2017
Kind
B2
Abstract

Disclosed herein is a display device including: a pixel array portion; a drive portion; and a power source wiring; the pixel array portion, at least a part of the drive portion configured to drive the pixel array portion and the power source wiring are forming a panel, the pixel array portion including scanning lines disposed in rows, signal lines disposed in columns, and pixels disposed in matrix in portions where the scanning lines and the signal lines cross each other, respectively, the drive portion including a scanner portion configured to drive the pixels in a line-sequential manner through the scanning lines, and a signal portion configured to supply a video signal to each of the signal lines in correspondence to the line-sequential drive, so that an image is displayed on the pixel array portion.

Claims (15)

1. A display device comprising a pixel array and a control circuitry;

the pixel array being disposed in a pixel array area and including:

a plurality of first lines disposed in a first direction,

a plurality of signal lines disposed in a second direction perpendicular to the first direction,

a plurality of pixels disposed in a matrix form;

the control circuitry including:

a first scanner circuit disposed in a first peripheral area adjacent to the pixel array area in the first direction, and configured to drive the plurality of first lines by supplying a pulse-like output voltage,

a signal circuit configured to drive the plurality of signal lines,

a potential wiring configured to supply a predetermined voltage to the pixels;

wherein at least a part of the potential wiring is disposed in a form of a multi-layer interconnection having at least a first wiring on a first layer and a second wiring on a second layer,

the first wiring is disposed at least in the first peripheral area and in a second peripheral area which is adjacent to the pixel array area in the second direction,

the first wiring extends along the second direction in the first peripheral area and along the first direction in the second peripheral area,

the second wiring is disposed so as to surround the pixel array area,

the first wiring and the second wiring are at least partially overlapping and electrically connected to each other in the first peripheral area,

wherein an area of the second wiring in a planar view of the pixel array is larger than an area of the first wiring in the planar view of the pixel array.

Assignments (1)
CONFIRMATORY LICENSE Recorded Jun 24, 2021
From: OCEANIT LABORATORIES, INC
To: THE GOVERNMENT OF THE UNITED STATES OF AMERICA AS REPRESENTED BY THE SECRETARY OF THE NAVY
Reel/Frame 056669/0806 →
Priority Claims (1)
JP 2006-238559 · Sep 4, 2006 · national
Continuity (2)
Continuation 11892726 · Aug 27, 2007
Related Publication 20160300529A1 · Oct 13, 2016