Three-dimensional semiconductor memory devices and methods of fabricating the same
Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.
1. A three-dimensional semiconductor device, comprising:
an electrode structure including a stacked plurality of electrodes on a substrate;
a plurality of semiconductor structures extending through the electrode structure; and
a plurality of memory elements between the semiconductor structures and the electrode structure, the memory elements including a tunnel insulating layer extending in a first direction beyond the plurality of electrodes and a blocking insulating layer extending in a second direction orthogonal to the first direction, wherein the first direction is perpendicular to a top surface of the substrate and the second direction is parallel to the top surface of the substrate.
2. The device of claim 1 , wherein the blocking insulating layer covers top and bottom surfaces of the plurality of electrodes.
3. The device of claim 1 , further comprising:
a plurality of interlayer insulating layers between the electrodes in the first direction,
wherein the tunnel insulating layer extends between sidewalls of the semiconductor structures and sidewalls of the electrodes, and between the sidewalls of the semiconductor structures and sidewalls of the interlayer insulating layers, and
the blocking insulating layer extends between the sidewalls of the semiconductor structures and the sidewalls of the electrodes, and between surfaces of the interlayer insulating layers.
4. The device of claim 3 , further comprising:
a capping layer between the semiconductor structures and the interlayer insulating layers, the capping layer being of a different material than the interlayer insulating layers.
5. The device of claim 4 , wherein the capping layer extends in the first direction between the electrodes and the semiconductor structures, and between the interlayer insulating layers and the semiconductor structures, and
the capping layer is thinner between the electrodes and the semiconductor structures than between the interlayer insulating layers and the semiconductor structures.
6. The device of claim 4 , wherein
the capping layer includes regions separated in the first direction by the blocking insulating layer.
7. The device of claim 1 , further comprising a charge storing layer, wherein:
the tunnel insulating layer is between the charge storing layer and the semiconductor structures,
the tunnel insulating layer includes at least one insulating layer,
the blocking insulating layer includes at least one insulating layer, and
the blocking insulating layer is between the charge storing layer and the electrodes.
8. The device of claim 7 , wherein
the charge storing layer extends in the second direction.
9. The device of claim 7 , wherein
the charge storing layer extends in the first direction.
10. The device of claim 9 , wherein the blocking insulating layer is a different material than the charge storing layer, and
the device further comprises a capping layer between the charge storing layer and the blocking insulating layer.
11. The device of claim 7 , wherein
at least one insulating layer of the tunnel insulating layer and at least one insulating layer of the blocking insulating layer include materials with a higher band gap than the charge storing layer, and
a dielectric constant of a material of at least one insulating layer of the blocking insulating layer is larger than a dielectric constant of a material of at least one insulating layer of the tunnel insulating layer.
12. The device of claim 7 , wherein
the tunnel insulating layer includes at least one silicon oxide layer,
the charge storing layer includes one of an insulating layer with a higher density of trap sites than a silicon oxide layer and an insulating layer with intrinsic conductive nano particles, and
the blocking insulating layer includes at least one of an aluminum oxide layer, a hafnium oxide layer, a zirconium oxide layer, a tantalum oxide layer, a titanium oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer.