IP Library › Granted Patent US 9,553,201
Granted Patent B2
US 9,553,201 · App. 14/179,452 · Granted Jan 24, 2017

Thin film transistor, thin film transistor array panel, and manufacturing method of thin film transistor

Inventors: Byung Du Ahn (Hwaseong-si, KR); Ji Hun Lim (Goyang-si, KR); Gun Hee Kim (Hwaseong-si, KR); Kyoung Won Lee (Ansan-si, KR); Je Hun Lee (Seoul, KR); Hiroshi Goto (Kobe, JP); Aya Miki (Kobe, JP); Shinya Morita (Kobe, JP); Toshihiro Kugimiya (Kobe, JP); Yeon Hong Kim (Yongin, KR); Yeon Gon Mo (Yongin, KR); Kwang Suk Kim (Yongin, KR)
Assignees: Samsung Display Co., Ltd.; Kobe Steel, Ltd.
H01L29/7869H01L29/78696
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Quick Facts
Patent No.
US 9,553,201
App. No.
14/179,452
Granted
Jan 24, 2017
Kind
B2
Abstract

The inventive concept relates to a thin film transistor and a thin film transistor array panel and, in detail, relates to a thin film transistor including an oxide semiconductor. A thin film transistor according to an exemplary embodiment of the inventive concept includes: a gate electrode; a gate insulating layer positioned on or under the gate electrode; a first semiconductor and a second semiconductor that overlap the gate electrode with the gate insulating layer interposed therebetween, the first semiconductor and the second semiconductor contacting each other; a source electrode connected to the second semiconductor; and a drain electrode connected to the second semiconductor and facing the source electrode, wherein the second semiconductor includes gallium (Ga) that is not included in the first semiconductor, and a content of gallium (Ga) in the second semiconductor is greater than 0 at. % and less than or equal to about 33 at. %.

Claims (47)

1. A thin film transistor comprising:

a gate electrode;

a gate insulating layer positioned on or under the gate electrode;

a first oxide semiconductor and a second oxide semiconductor that overlap the gate electrode with the gate insulating layer interposed therebetween, an overlapping area of the first oxide semiconductor and the gate electrode being substantially the same as an overlapping area of the second oxide semiconductor and the gate electrode, a composition of the second oxide semiconductor being different from a composition of the first oxide semiconductor;

a source electrode connected to the second oxide semiconductor, the source electrode contacting an upper surface of the second oxide semiconductor, the upper surface being a surface opposite to an interface between the first oxide semiconductor and the second oxide semiconductor; and

a drain electrode connected to the second oxide semiconductor and facing the source electrode,

wherein the second oxide semiconductor includes gallium (Ga) and the first oxide semiconductor does not include gallium, and

a content of gallium (Ga) in the second oxide semiconductor is greater than 0 at. % and less than or equal to about 33 at. %.

2. The thin film transistor of claim 1 , wherein

the first oxide semiconductor and the second oxide semiconductor respectively include indium (In)-tin (Sn)-zinc (Zn) oxide (IZTO).

3. The thin film transistor of claim 2 , wherein

a content ratio of zinc (Zn) to tin (Sn) included in the first oxide semiconductor is substantially the same as a content ratio of zinc (Zn) to tin (Sn) included in the second oxide semiconductor.

4. The thin film transistor of claim 3 , wherein

etch rates of the first oxide semiconductor and the second oxide semiconductor in a same etchant are substantially the same.

5. The thin film transistor of claim 2 , wherein

etch rates of the first oxide semiconductor and the second oxide semiconductor in a same etchant are substantially the same.

6. The thin film transistor of claim 1 ,

wherein the first oxide semiconductor and the second oxide semiconductor include tin (Sn) and zinc, and

wherein a content ratio of zinc (Zn) to tin (Sn) included in the first oxide semiconductor is substantially the same as a content ratio of zinc (Zn) to tin (Sn) included in the second oxide semiconductor.

7. The thin film transistor of claim 6 , wherein

etch rates of the first oxide semiconductor and the second semiconductor in a same etchant are substantially the same.

8. The thin film transistor of claim 6 , wherein

etching rates of the first oxide semiconductor and the second oxide semiconductor in a same etchant are substantially the same.

9. A thin film transistor array panel comprising the thin film transistor of claim 1 .

10. A thin film transistor comprising:

a gate electrode;

a semiconductive layer overlapping the gate electrode with a gate insulating layer interposed between the gate electrode and the semiconductive layer, wherein the semiconductive layer includes a first semiconductor and a second semiconductor, an overlapping area of the first semiconductor and the gate electrode being substantially the same as an overlapping area of the second semiconductor and the gate electrode, a composition of the second semiconductor being different from a composition of the first semiconductor;

a source electrode connected to the second semiconductor; and

a drain electrode connected to the second semiconductor and facing the source electrode,

wherein the first semiconductor and the second semiconductor include tin and zinc, and

wherein a content ratio of zinc (Zn) to tin (Sn) included in the first semiconductor is substantially the same as a content ratio of zinc (Zn) to tin (Sn) included in the second semiconductor, and

wherein the second semiconductor includes gallium (Ga), and the first semiconductor does not include gallium.

11. The thin film transistor of claim 10 , wherein

the second semiconductor includes gallium (Ga) that is not included in the first semiconductor, and

a content of gallium (Ga) in the second semiconductor is greater than 0 at. % and less than or equal to about 33 at. %.

12. The thin film transistor of claim 11 , wherein

the first semiconductor and the second semiconductor respectively include indium (In)-tin (Sn)-zinc (Zn) oxide (IZTO).

13. The thin film transistor of claim 12 , wherein

etch rates of the first semiconductor and the second semiconductor in a same etchant are substantially the same.

14. The thin film transistor of claim 11 , wherein

etch rates of the first semiconductor and the second semiconductor in a same etchant are substantially the same.

15. The thin film transistor of claim 10 , wherein

the first semiconductor and the second semiconductor respectively include indium (In)-tin (Sn)-zinc (Zn) oxide (IZTO).

16. The thin film transistor of claim 15 , wherein

etch rates of the first semiconductor and the second semiconductor in a same etchant are substantially the same.

17. The thin film transistor of claim 10 , wherein

etch rates of the first semiconductor and the second semiconductor in a same etchant are substantially the same.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2022
From: KABUSHIKI KAISHA KOBE SEIKO SHO
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 061700/0110 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 27, 2016
From: AHN, BYUNG DU; LIM, JI HUN; KIM, GUN HEE; LEE, KYOUNG WON; KIM, YEON HONG; LEE, JE HUN; MO, YEON GON; KIM, KWANG SUK
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 039019/0399 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 27, 2016
From: GOTO, HIROSHI; MIKI, AYA; MORITA, SHINYA; KUGIMIYA, TOSHIHIRO
To: KABUSHIKI KAISHA KOBE SEIKO SHO (KOBE STEEL, LTD.)
Reel/Frame 039019/0484 →
Priority Claims (2)
KR 10-2012-0034101 · Apr 2, 2012 · national
KR 10-2013-0108687 · Sep 10, 2013 · national
Continuity (2)
Continuation In Part 13555889 · Jul 23, 2012
Related Publication 20140167038A1 · Jun 19, 2014