Inter-block scan testing with share pads
An integrated circuit (IC) chip includes a first circuit block, a second circuit block, an inter-block circuit and a control circuit. The first circuit block is configured to form a first scan chain to set states of flip-flops in the first circuit block. The second circuit block is configured to form a second scan chain to set states of flip-flops in the second circuit block. The inter-block circuit interfaces the first circuit block and the second circuit block. The control circuit is configured to load a first portion and a second portion of a test pattern separately to the first scan chain and the second scan chain to set states of flip-flops in the first circuit block and the second circuit block, enable a test of the inter-block circuit to capture a test result, and unload the test result from the first scan chain and the second scan chain.
1. An integrated circuit (IC) chip, comprising:
a first circuit block configured to form a first scan chain in a test mode to set states of flip-flops in the first circuit block;
a second circuit block, separate from the first circuit block, configured to form a second scan chain in a test mode to set states of flip-flops in the second circuit block;
an inter-block circuit having logic circuits that interface the first circuit block and the second circuit block; and
a control circuit configured to load a first portion and a second portion of a test pattern for the inter-block circuit separately to the first scan chain and the second scan chain to set states of flip-flops in both the first circuit block and the second circuit block, enable a test of the inter-block circuit to capture a test result of the inter-block circuit in the flip-flops of the first circuit block and the second circuit block, and unload the test result of the inter-block circuit from the first scan chain and the second scan chain.
2. The IC chip of claim 1 , comprising:
a first pad that is configured to receive a bit stream of the test pattern that combines the first portion and the second portion; and wherein
the control circuit is configured to separate the first portion and the second portion, and provide the first portion to the first circuit block and the second portion to the second circuit block.
3. The IC chip of claim 2 , further comprising:
a second pad that is configured to output the test result unloaded from the first scan chain and the second scan chain.
4. The IC chip of claim 2 , wherein the control circuit comprises:
a de-multiplexer configured to receive the bit stream and output bits respectively to the first circuit block and to the second circuit block based on a selector signal.
5. The IC chip of claim 4 , wherein the control circuit comprises:
a clock control circuit configured to provide clock signals respectively to the first circuit block and to the second circuit block based on the selector signal.
6. The IC chip of claim 5 , further comprising:
a third pad that is configured to receive the selector signal from an external source, and to provide the selector signal to the de-multiplexer and the clock control circuit.
7. The IC chip of claim 5 , comprising:
a selector circuit that is configured to generate the selector signal for the de-multiplexer and the clock control circuit.