IP Library Granted Patent US 9,563,430
Granted Patent B2
US 9,563,430 · App. 14/219,565 · Granted Feb 7, 2017

Dynamic thread sharing in branch prediction structures

Inventors: James J. Bonanno (Wappingers Falls, NY); Daniel Lipetz (Flushing, NY); Brian R. Prasky (Campbell Hall, NY); Anthony Saporito (Highland, NY)
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
G06F9/3861G06F9/30058G06F9/3806G06F9/3851G06F9/3844
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Quick Facts
Patent No.
US 9,563,430
App. No.
14/219,565
Granted
Feb 7, 2017
Kind
B2
Abstract

Embodiments relate to multithreaded branch prediction. An aspect includes a system for dynamically evaluating how to share entries of a multithreaded branch prediction structure. The system includes a first-level branch target buffer coupled to a processor circuit. The processor circuit is configured to perform a method. The method includes receiving a search request to locate branch prediction information associated with the search request, and searching for an entry corresponding to the search request in the first-level branch prediction structure. The entry is not allowed based on a thread state of the entry indicating that the entry has caused a problem on a thread associated with the thread state.

Claims (49)

1. A computer system for dynamically evaluating how to share,

among threads that are being tracked in a processor circuit, entries of a multithreaded branch prediction structure, the system comprising:

a first-level branch prediction structure; and

said processor circuit communicatively coupled to the first-level branch prediction structure, wherein the computer system is configured to perform operations comprising:

receiving a search request to locate branch prediction information associated with said search request;

searching, by the processor circuit, in the first-level branch prediction structure for conditionally matching first-level entries corresponding to the search request, said first level entries each including a thread state;

wherein the thread state comprises a first thread state portion having at least one data field that identifies either a share-state or a no-share state of threads that are being tracked in the processor circuit;

wherein the thread state further comprises a second thread state portion having at least one data field that identifies context thread information of threads that are being tracked in the processor circuit,

wherein conditionally matching first-level entries corresponding to the search request comprises satisfying either of a first condition or a second condition,

wherein satisfying said first condition comprises determining that said at least one data field of said first thread state portion identifies said share-state;

wherein satisfying second first condition comprises determining that said second thread state portion matches a portion of the search request;

initially allowing branch predictions, by said processor circuit, of said conditionally matching first-level entries; and

not allowing branch predictions, by said processor circuit, of specific ones of said conditionally matching first-level entries based on determining that said branch predictions of specific ones of said conditionally matching first-level entries previously caused a problem on at least one of threads corresponding to said thread states of said specific ones of said conditionally matching first-level entries.

2. The system of claim 1 further comprising, in response to said problem, updating said first thread states portion of said each first-level entries.

3. The system of claim 1 wherein said problem comprises a bad branch presence prediction associated with said at least one of the threads.

4. The system of claim 1 wherein said first portion of said thread state comprises a thread sharing data field.

5. The system of claim 1 wherein said at least one data field that identifies context thread information comprises a thread context tag.

6. The system of claim 5 wherein:

said determining that said branch predictions of specific ones of said conditionally matching first-level entries previously caused said problem comprises identifying a conflict mode; and

said conflict mode comprises a mismatch between said thread context tag and said context state information.

7. The system of claim 1 wherein the branch prediction structure is hierarchical, the system further comprising:

a second-level branch prediction structure; and

the processor circuit communicatively coupled to the second-level branch prediction structure, wherein the method performed by the system further comprises:

based on failing to locate a matching first-level entry in the first-level branch prediction structure corresponding to the search request, initiating, by the processor circuit, a secondary search to locate matching second-level entries in the second-level branch prediction structure;

wherein said second level entries each includes a second-level thread state;

initially allowing branch predictions, by said processor circuit, of said conditionally matching second-level entries; and

not allowing branch predictions, by said processor circuit, of specific ones of said conditionally matching second-level entries based on second-level thread states of said second-level specific ones indicating that said branch predictions of si second-level specific ones of said conditionally matching second-level entries previously caused a problem on at least one of the threads corresponding to said second-level thread states.

8. A computer program product for dynamically evaluating how to share, among threads that are being tracked in a processor circuit, entries of a multithreaded branch prediction structure, the computer program product comprising:

a computer readable storage medium having program instructions embodied therewith, wherein the computer readable storage medium is not a signal, the program instructions readable by a processor circuit to cause the processor circuit to perform a method comprising:

receiving a search request to locate branch prediction information associated with said search request;

searching, by a processor circuit, in a first-level branch prediction structure for conditionally matching first-level entries corresponding to the search request;

said first-level entries each including a thread state;

wherein the thread state comprises a first thread state portion having at least one data field that identifies either a share-state or a no-share state of threads that are being tracked in the processor circuit;

wherein the thread state further comprises a second thread state portion having at least one data field that identifies context thread information of threads that are being tracked in the processor circuit,

wherein conditionally matching first-level entries corresponding to the search request comprises satisfying either of a first condition or a second condition;

wherein satisfying said first condition comprises determining that said at least one data field of said first thread state portion identifies said share-state;

wherein satisfying second first condition comprises determining that said second thread state portion matches a portion of the search request,

initially allowing branch predictions, by the processor circuit, of said conditionally matching first-level entries; and

not allowing branch predictions, by said processor circuit, of specific ones of said conditionally matching first-level entries based on thread states of said specific ones of said conditionally matching first level entries indicating that said specific ones of said conditionally matching first-level entries previously caused a problem on at least one of threads corresponding to said thread states of said specific ones of said conditionally matching first-level entries.

9. The computer program product of claim 8 further comprising, in response to said problem, updating first thread said thread state portion of said each first-level entries.

10. The computer program product of claim 8 wherein said problem comprises a bad branch presence prediction associated with said at least one of the threads.

11. The computer program product of claim 8 wherein:

said branch prediction structure is hierarchical and includes:

a second-level branch prediction structure; and

the processor circuit communicatively coupled to the second-level branch prediction structure, wherein the method performed by the system further comprises:

based on failing to locate a matching first-level entry in the first-level branch prediction structure corresponding to the search request, initiating, by the processor circuit, a secondary search to locate matching second-level entries in the second-level branch prediction structure;

said second level entries each including a second-level thread state;

initially allowing, by said processor circuit, said conditionally matching second-level entries; and

not allowing, by said processor circuit, specific ones of said conditionally matching second-level entries based on second-level thread states of second-level specific ones of said conditionally matching second-level entries indicating that said second-level specific ones of said conditionally matching second-level entries previously caused a problem on at least one of the threads corresponding to said second-level thread states.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 19, 2014
From: BONANNO, JAMES J.; LIPETZ, DANIEL; PRASKY, BRIAN R.; SAPORITO, ANTHONY
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 032476/0698 →
Continuity (1)
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