IP Library › Granted Patent US 9,571,089
Granted Patent B2
US 9,571,089 · App. 14/518,470 · Granted Feb 14, 2017

Built-in gate driver

Inventors: Yong Ho Jang (Goyang-si, KR); Woo Seok Choi (Paju-si, KR)
Assignee: LG Display Co., Ltd.
H03K17/161
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Quick Facts
Patent No.
US 9,571,089
App. No.
14/518,470
Granted
Feb 14, 2017
Kind
B2
Abstract

A built-in gate driver includes a shift register provided in a non-display area of a panel, and configured to include first to gth stages outputting a scan signal, a clock supply line part configured to include m number of clock supply lines connected to the shift register, and a power supply line part configured to include n number of power supply lines connected to the shift register. At least one of the lines of the clock supply lines and the power supply lines are in a first side direction of the shift register, and the other at least one or more lines of the clock supply lines and the power supply lines are in a second side direction of the shift register.

Claims (40)

1. A built-in gate driver comprising:

a shift register provided in a non-display area of a panel, and including first to gth stages outputting a scan signal;

a clock supply line part including m number of clock supply lines connected to the shift register; and

a power supply line part configured including n number of power supply lines connected to the shift register,

wherein at least one or more lines of the m clock supply lines and the n power supply lines are disposed in a first side direction of the shift register, and

the other of the m lines of the clock supply lines and the n power supply lines are disposed in a second side direction of the shift register; and

n and m are each natural numbers greater than 2.

2. The built-in gate driver of claim 1 , wherein,

the m clock supply lines are in the first side direction of the shift register, and the first side direction is an outer direction of the panel, and

the n power supply lines are in the second side direction of the shift register, and the second side direction is adjacent to a display area of the panel.

3. The built-in gate driver of claim 1 , wherein,

the n power supply lines are in the first side direction of the shift register, and the first side direction is an outer direction of the panel, and

the m clock supply lines are in the second side direction of the shift register, and the second side direction is adjacent to a display area of the panel.

4. The built-in gate driver of claim 1 , wherein,

the m clock supply lines and at least one of the n power supply lines are in the first side direction of the shift register, and the first side direction is an outer direction of the panel, and

among the n power supply lines, power supply lines except a power supply line in the first side direction are in the second side direction of the shift register, and the second side direction is adjacent to a display area of the panel.

5. The built-in gate driver of claim 1 , wherein,

the n power supply lines and at least one of the m clock supply lines are in the second side direction of the shift register, and the second side direction is adjacent to a display area of the panel, and

among the m clock supply lines, clock supply lines except the clock supply line in the second side direction are in the first side direction of the shift register, and the first side direction is an outer direction of the panel.

6. The built-in gate driver of claim 1 , wherein,

the n power supply lines and at least one of the m clock supply lines are in the first side direction of the shift register, and the first side direction is an outer direction of the panel, and

among the m clock supply lines, clock supply lines except the clock supply line in the first side direction are in the second side direction of the shift register, and the second side direction is adjacent to a display area of the panel.

7. The built-in gate driver of claim 1 , wherein,

the m clock supply lines and at least one of the n power supply lines are in the second side direction of the shift register, and the second side direction is adjacent to a display area of the panel, and

among the n power supply lines, power supply lines except a power supply line in the second side direction are in the first side direction of the shift register, and the first side direction is the outer direction of the panel.

8. A built-in gate driver comprising:

a shift register provided in a non-display area of a panel, and including first to gth stages outputting a scan signal, each of the stages having at least two scan signal output units;

a clock supply line part including m number of clock supply lines connected to the shift register; and

a power supply line part configured including n number of power supply lines connected to the shift register,

wherein,

the at least two scan signal output units are connected to two or more gate lines which are disposed along one horizontal line of the panel, and output two or more scan signals to a plurality of gate lines; and

the m clock supply lines or the n power supply lines are disposed in a first and a second side direction with respect to the shift register,

the first side direction is an outer direction of the panel,

the second side direction is adjacent to a display area of the panel, and

the other of the m clock supply lines and the n power supply lines are disposed between the at least two scan signal output units of a stage of the stages.

9. The built-in gate driver of claim 1 , wherein,

each of the clock supply lines and the power supply lines comprises a main line along an outer direction of the panel and a branch line configured to electrically connect the main line to the shift register,

a plurality of the branch lines are on the same layer as a layer of a gate electrode of a thin film transistor (TFT) formed in the stage, or on the same layer as a layer of a source electrode and drain electrode of the TFT, and

the main line and the branch line are on different layers.

10. The built-in gate driver of claim 1 , wherein a pull-up transistor, which is in the stage and outputs a pull-up signal of the scan signal, is in a coplanar type.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 20, 2014
From: JANG, YONG HO; CHOI, WOO SEOK
To: LG DISPLAY CO., LTD.
Reel/Frame 033983/0330 →
Priority Claims (1)
KR 10-2013-0128964 · Oct 29, 2013 · national
Continuity (1)
Related Publication 20150116008A1 · Apr 30, 2015