IP Library Granted Patent US 9,577,659
Granted Patent B2
US 9,577,659 · App. 15/163,916 · Granted Feb 21, 2017

Amplifier circuit, ad converter, wireless communication device, and sensor system

Inventors: Kentaro Yoshioka (Tokyo, JP); Masanori Furuta (Kanagawa, JP); Junya Matsuno (Kanagawa, JP); Tetsuro Itakura (Tokyo, JP)
Assignee: KABUSHIKI KAISHA TOSHIBA
H03M1/124H03F1/34H03F3/45H03K3/0315H03F2200/294H04W88/02
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Quick Facts
Patent No.
US 9,577,659
App. No.
15/163,916
Granted
Feb 21, 2017
Kind
B2
Abstract

An amplifier circuit has a sampling circuit to comprise a sampling capacitor which samples an input voltage and a plurality of switches, a quantizer to quantize an output voltage of the sampling circuit, a DA converter to output an analog signal depending on a quantization signal by the quantizer, and a feedback capacitor to feed the analog signal back to the output voltage of the sampling circuit.

Claims (26)

1. An amplifier circuit, comprising:

a sampling circuit including a sampling capacitor which samples an input voltage and a plurality of switches;

a quantizer to quantize an output voltage of the sampling circuit;

a DA converter to output an analog signal depending on a quantization signal by the quantizer, and

a feedback capacitor to feed the analog signal back to the output voltage of the sampling circuit, the feedback capacitor being connected in series to the sampling capacitor.

2. The amplifier circuit of claim 1 , further comprising a digital calculation circuit to multiply the quantization signal by −K and input the multiplied quantization signal into the DA converter.

3. The amplifier circuit of claim 1 , wherein the quantizer is a successive approximation AD converter to comprise a first comparator which compares the output voltage of the sampling circuit with a ground voltage, and a logic circuit which controls the first comparator.

4. The amplifier circuit of claim 1 , wherein the DA converter is a capacitor DAC or a resistance DAC.

5. The amplifier circuit of claim 1 , further comprising a reset switch to reset the feedback capacitor.

6. The amplifier circuit of claim 1 , further comprising:

a first switch to be connected between the sampling circuit and the feedback capacitor, and

a second switch to be connected between the feedback capacitor and the DA converter.

7. The amplifier circuit of claim 6 , wherein the first switch is used also as a switch of a sampling circuit connected in a subsequent stage.

8. The amplifier circuit of claim 7 ,

wherein the DA converter is a capacitor DAC to comprise a capacitor element, and

the capacitor element is used also as a sampling capacitor of the sampling circuit connected in the subsequent stage.

9. The amplifier circuit of claim 1 , further comprising an amplifier to amplify the output voltage of the sampling circuit and input the amplified voltage into the feedback capacitor.

10. The amplifier circuit of claim 9 , wherein the amplifier comprises a second comparator to compare the output voltage of the sampling circuit with a ground voltage, and a current source to supply current to the feedback capacitor depending on an output signal of the second comparator.

11. The amplifier circuit of claim 9 , wherein the amplifier comprises an operational amplifier to amplify the output voltage of the sampling circuit, and a third switch to stop an output of the operational amplifier.

12. The amplifier circuit of claim 11 , wherein the third switch is connected between an output terminal of the operational amplifier and the feedback capacitor.

13. The amplifier circuit of claim 11 , wherein the third switch is provided on a power-supply line of the operational amplifier.

14. The amplifier circuit of claim 11 , further comprising a pulse generator to generate a clock which opens and closes the third switch.

15. The amplifier circuit of claim 9 , wherein the amplifier comprises a ring amplifier to amplify the output voltage of the sampling circuit, and a counter to count the number of oscillations of the ring amplifier.

16. An AD converter comprising the amplifier circuit of claim 1 .

17. A wireless communication device comprising the AD converter of claim 16 .

18. A sensor system comprising the AD converter of claim 16 .

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 12, 2016
From: YOSHIOKA, KENTARO; FURUTA, MASANORI; MATSUNO, JUNYA; ITAKURA, TETSURO
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 039417/0069 →
Priority Claims (1)
JP 2015-110647 · May 29, 2015 · national
Continuity (1)
Related Publication 20160352349A1 · Dec 1, 2016