Method for manufacturing injection-enhanced insulated-gate bipolar transistor
A method for manufacturing an injection-enhanced insulated-gate bipolar transistor, comprising the following steps: an n-type substrate ( 12 ) is provided; a p-type doped layer ( 14 ) is formed on the n-type substrate ( 12 ); a hard layer ( 20 ) is formed on the p-type doped layer ( 14 ); a groove ( 40 ) extending to the n-type substrate ( 12 ) is formed by etching on the p-type doped layer ( 14 ); an n-type doped layer ( 50 ) is formed on the sidewalls and bottom of the groove ( 40 ); the hard layer ( 20 ) is removed; p-type impurities of the p-type doped layer ( 14 ) and n-type impurities of the n-type doped layer ( 50 ) are driven in together, where the p-type impurities are diffused to form a p-type base region ( 60 ), and the n-type impurities are diffused to form an n-type buffer layer ( 70 ); a gated oxide dielectric layer ( 80 ) is formed on the surface of the groove ( 40 ); and, a polysilicon layer ( 90 ) is deposited in the groove having formed therein the gate oxide dielectric layer ( 80 ). In the method for manufacturing the injection-enhanced insulated-gate bipolar transistor, the p-type doped layer ( 14 ) and the n-type doped layer ( 50 ) are driven in together to form the p-type base region ( 60 ) and the n-type buffer layer ( 70 ), as only one drive-in process is required, production cycle is shortened in comparison with a conventional method for manufacturing the injection-enhanced insulated-gate bipolar transistor.
1. A method of manufacturing an injection enhanced IGBT (Insulated Gate Bipolar Transistor), comprising steps as follow:
providing an N-type substrate;
forming a P-type doped layer on the N-type substrate;
forming a hard layer on the P-type doped layer;
etching the hard layer to form a hard layer having a trench pattern;
etching the P-type doped layer to form a trench extending into the N-type substrate;
forming an N-type doped layer on a sidewall and a bottom of the trench;
removing the hard layer having the trench pattern;
performing a drive-in to the P-type dopant of the P-type doped layer and the N-type dopant of the N-type doped layer together, the P-type dopant forming a P-type base region by diffusing, and the N-type dopant forming an N-type buffer layer by diffusing;
forming a gate oxide dielectric layer on a surface of the trench; and
depositing a polysilicon layer in the trench on which the gate oxide dielectric layer is formed.
2. The method of manufacturing the injection-enhanced IGBT according to claim 1 , wherein the P-type doped layer is formed by ion implantation or diffusion.
3. The method of manufacturing the injection-enhanced IGBT according to claim 2 , wherein a concentration of P-type dopant in the P-type doped layer is from 1×10 12 /cm 3 to 1×10 20 /cm 3 .
4. The method of manufacturing the injection-enhanced IGBT according to claim 1 , wherein in the forming the N-type doped layer on the sidewall and the bottom of the trench, the hard layer is adopted as a mask, the N-type doped layer is formed by diffusion technology.
5. The method of manufacturing the injection-enhanced IGBT according to claim 1 , wherein a concentration of N-type dopant in the N-type doped layer is 1×10 12 /cm 3 to 1×10 20 /cm 3 .
6. The method of manufacturing the injection-enhanced IGBT according to claim 1 , wherein in the performing a drive-in to the P-type dopant of the P-type doped layer and the N-type dopant of the N-type doped layer together, a temperature of the drive-in is from 1100° C to 1280° C.
7. The method of manufacturing the injection-enhanced IGBT according to claim 1 , wherein in the performing a drive-in to the P-type dopant of the P-type doped layer and the N-type dopant of the N-type doped layer together, a time period of the drive-in is from 20 min to 500 min.
8. The method of manufacturing the injection-enhanced IGBT according to claim 1 , wherein the forming the gate oxide dielectric layer on the surface of the trench comprises:
oxidizing the surface of the trench to form a sacrificial oxide layer;
removing the sacrificial oxide layer by etching;
oxidizing the surface of the trench to form the gate oxide dielectric layer.
9. The method of manufacturing the injection-enhanced IGBT according to claim 1 , wherein the hard layer is made of silicon oxide or silicon nitride.
10. A method of manufacturing the injection-enhanced IGBT, comprising steps as follow:
providing an N-type substrate;
forming a hard layer on the N-type doped layer;
etching the hard layer to form a hard layer having a trench pattern;
etching the N-type doped layer to form a trench;
forming an N-type doped layer on a sidewall and a bottom of the trench;
removing the hard layer having the trench pattern;
forming a mask layer in the trench, the mask layer filling the trench;
forming a P-type doped layer on a surface of the N-type substrate which forms the trench;
removing the mask layer;
performing a drive-in to the P-type dopant of the P-type doped layer and the N-type dopant of the N-type doped layer together, the P-type dopant forming a P-type base region by diffusing, and the N-type dopant forming an N-type buffer layer by diffusing;
forming a gate oxide dielectric layer on a surface of the trench; and
depositing a polysilicon layer in the trench on which the gate oxide dielectric layer is formed.