p-FET with strained silicon-germanium channel

1. A method of forming a semiconductor structure, comprising:

forming a dummy gate above a semiconductor substrate, the dummy gate defining a source-drain region adjacent to the dummy gate and a silicon channel region below the dummy gate;

epitaxially growing a silicon-germanium layer above the source-drain region, the silicon-germanium layer having a target concentration of germanium atoms;

annealing the semiconductor structure to diffuse germanium atoms from the silicon-germanium layer into the silicon channel region to form a silicon-germanium channel region; and

removing the silicon-germanium layer from above the source-drain region;

forming a doped epitaxial layer adjacent to the silicon-germanium channel region to form a raised source-drain region;

wherein forming the doped epitaxial layer comprises epitaxially growing in-situ boron doped silicon-germanium or in-situ boron doped silicon.

2. The method of claim 1 , wherein the silicon-germanium channel region has substantially unvarying dimensions.

3. The method of claim 1 , wherein annealing the semiconductor structure comprises conducting a high temperature anneal to accomplish a homogenous distribution of germanium atoms throughout the silicon-germanium channel region.

4. A method of forming a semiconductor structure, comprising:

forming a dummy gate above a semiconductor substrate, the semiconductor substrate including an n-FET region and a p-FET region;

masking the n-FET region of the semiconductor substrate;

epitaxially growing a silicon-germanium layer above a portion of the semiconductor substrate in the p-FET region not covered by the dummy gate, the silicon-germanium layer having a target concentration of germanium atoms;

annealing the semiconductor structure to a temperature sufficient to cause germanium atoms from the silicon-germanium layer to diffuse into a portion of the semiconductor substrate below the dummy gate to form a silicon-germanium channel region;

removing the silicon-germanium layer selective to the portion of the semiconductor substrate not covered by the dummy gate;

etching the portion of the semiconductor substrate not covered by the dummy gate to reduce a thickness of the portion of the semiconductor substrate not covered by the dummy gate; and

growing a p-doped epitaxial layer adjacent to the silicon-germanium channel region to form a raised source-drain region.

5. The method of claim 4 , wherein forming the dummy gate above the semiconductor substrate comprises forming the dummy gate above an extremely thin semiconductor-on-insulator (ETSOI) substrate.

6. The method of claim 4 , wherein forming the dummy gate above the semiconductor substrate comprises forming the dummy gate around a fin formed from the semiconductor substrate.

7. The method of claim 4 , wherein forming the dummy gate above the semiconductor substrate comprises forming the dummy gate surrounding a nanowire structure formed from the semiconductor substrate.

8. The method of claim 4 , wherein the target concentration of germanium ranges from approximately 40% to approximately 60% of germanium.

9. The method of claim 4 , wherein annealing the semiconductor structure comprises conducting a high temperature anneal to accomplish a homogenous distribution of germanium atoms throughout the silicon-germanium channel region.

10. The method of claim 4 , wherein the dummy gate physically protects the channel region during diffusion of germanium atoms so that dimensions of the silicon-germanium channel region remain unvarying.

11. The method of claim 4 , wherein a p-FET device formed in the p-FET region of the semiconductor substrate has a silicon-germanium channel region with substantially the same dimensions as a silicon channel region of an n-FET device formed in the n-FET region of the semiconductor substrate.

12. The method of claim 4 , wherein growing the p-doped epitaxial layer comprises epitaxially growing an in-situ boron doped silicon-germanium material.

13. A method of forming a semiconductor structure, comprising:

forming a dummy gate above a semiconductor substrate, the semiconductor substrate including an n-FET region and a p-FET region;

masking the n-FET region of the semiconductor substrate;

epitaxially growing a silicon-germanium layer above a portion of the semiconductor substrate in the p-FET region not covered by the dummy gate;

annealing the semiconductor structure to a temperature sufficient to cause germanium atoms from the silicon-germanium layer to diffuse into a portion of the semiconductor substrate below the dummy gate to form a silicon-germanium channel region in the p-FET region;

removing the silicon-germanium layer selective to the semiconductor substrate; and

growing a p-doped epitaxial layer adjacent to the silicon-germanium channel region to form a raised source-drain region.

14. The method of claim 13 , wherein the germanium concertation of the silicon-germanium layer ranges from approximately 40% to approximately 60% of germanium.

15. The method of claim 13 , wherein annealing the semiconductor structure comprises conducting a high temperature anneal to accomplish a homogenous distribution of germanium atoms throughout the silicon-germanium channel region.

16. The method of claim 13 , wherein the dummy gate physically protects the channel region during diffusion of germanium atoms so that dimensions of the silicon-germanium channel region remain unvarying.

17. The method of claim 13 , wherein dimensions of the silicon-germanium channel region in the p-FET region are substantially the same as dimensions of a silicon channel region formed in the n-FET region.

18. The method of claim 13 , wherein growing the p-doped epitaxial layer comprises epitaxially growing an in-situ boron doped silicon-germanium material.