Apparatus and method for digitally cancelling crosstalk
Described is an apparatus which comprises: a first buffer to receive a first signal from a first transmission media; a second buffer to receive a second signal from a second transmission media separate from the first transmission media; a first summing node coupled to the first buffer, the first summing node to receive output of the first buffer; and a first digital adjustment circuit which is operable to drive a first adjustment signal to the first summing node when a transition edge of the second signal is detected.
1. An apparatus comprising:
a first buffer associated with a first receiver, the first buffer is to receive a first signal from a first transmission media;
a second buffer associated with a second receiver, the second buffer is to receive a second signal from a second transmission media separate from the first transmission media;
a first summing node coupled to the first buffer, the first summing node to receive output of the first buffer; and
a first digital adjustment circuit which is operable to drive a first adjustment signal to the first summing node when a transition edge of the second signal is detected.
2. The apparatus of claim 1 , wherein the first buffer and the first digital adjustment circuit are to have substantially the same propagation delays.
3. The apparatus of claim 1 , wherein the first digital adjustment circuit comprises:
a pulse generator to receive the second signal and to generate a pulse; and
a tri-stable buffer which is operable to buffer the second signal as the first adjustment signal according to a duration of the pulse.
4. The apparatus of claim 1 comprises:
a second summing node coupled to the second buffer, wherein the second summing node is to receive output of the second buffer.
5. The apparatus of claim 3 , wherein the pulse generator has a programmable delay buffer.
6. The apparatus of claim 4 comprises:
a second digital adjustment circuit which is operable to drive a second adjustment signal to the second summing node when a transition edge of the first signal is detected.
7. The apparatus of claim 6 , wherein the second buffer and the second digital adjustment circuit are to have substantially the same propagation delays.
8. The apparatus of claim 6 , wherein the second digital adjustment circuit comprises:
a pulse generator to receive the first signal and to generate a pulse; and
a tri-stable buffer which is operable to buffer the first signal as the second adjustment signal according to a duration of the pulse.
9. The apparatus of claim 8 , wherein the pulse generator has a programmable delay buffer.
10. The apparatus of claim 4 comprises:
a first capacitive device coupled to the first summing node; and
a second capacitive device coupled to the second summing node.
11. An apparatus comprising:
a bus to provide first and second signals; and
a pair of cross-coupled digital adjustment circuits which are operable to:
drive a first adjustment signal to a first summing node when a transition edge of the second signal is detected, and
drive a second adjustment signal to a second summing node when a transition edge of the first signal is detected.
12. The apparatus of claim 11 , wherein one of the cross-coupled digital adjustment circuit comprises:
a pulse generator to receive the second signal and to generate a pulse; and
a tri-stable buffer which is operable to buffer the second signal as the first adjustment signal according to a duration of the pulse.
13. The apparatus of claim 11 , wherein another of the cross-coupled digital adjustment circuit comprises:
a pulse generator to receive the first signal and to generate a pulse; and
a tri-stable buffer which is operable to buffer the first signal as the second adjustment signal according to a duration of the pulse.
14. The apparatus of claim 11 comprises:
a first buffer to receive the first signal from a first transmission media of the bus; and
a second buffer to receive a second signal from a second transmission media of the bus, wherein the second transmission media is separate from the first transmission media.
15. A system comprising:
a memory;
a processor coupled to the memory by a bus having first and second transmission lines to provide first and second signals, respectively, the processor including a receiver which comprises:
a pair of cross-coupled digital adjustment circuits which are operable to:
drive a first adjustment signal to a first summing node when a transition edge of the second signal is detected, and
drive a second adjustment signal to a second summing node when a transition edge of the first signal is detected; and
a wireless interface for allowing the processor to communicate with another device.
16. The system of claim 15 , wherein the receiver is a Double Data Rate (DDR) compliant receiver.
17. The system of claim 15 , wherein one of the cross-coupled digital adjustment circuit comprises:
a pulse generator to receive the second signal and to generate a pulse; and
a tri-stable buffer which is operable to buffer the second signal as the first adjustment signal according to a duration of the pulse.
18. The system of claim 17 , wherein another of the cross-coupled digital adjustment circuit comprises:
a pulse generator to receive the first signal and to generate a pulse; and
a tri-stable buffer which is operable to buffer the first signal as the second adjustment signal according to a duration of the pulse.
19. The system of claim 15 , wherein the receiver comprises:
a first buffer to receive the first signal from a first transmission media of the bus; and
a second buffer to receive a second signal from a second transmission media of the bus, wherein the second transmission media is separate from the first transmission media.
20. The system of claim 15 further comprises a display interface for allowing a display unit to display content processed by the processor.