Information processing device with shared memory, memory order guarantee method using counters fence instructions in relation to cache-oriented requests, and recording medium storing program

1. An information processing device comprising:

a plurality of processors including an Acquire side processor intending to read data and a Release side processor intending to write data; and

a shared memory,

the Acquire side processor and the Release side processor including

a cache,

a memory access control unit configured to control access from the processors to the shared memory, the memory access control unit in the Release side processor, configured to comprise a store counter whose value is increased if a Store instruction is issued to the shared memory, and is decreased if an acknowledgement response indicating correct reception of the Store instruction is received from the shared memory, and a wait counter whose value is set at a value representing a predetermined time if the store counter has come to indicate 0, the wait counter decreasing the value at every predetermined interval, and the predetermined time being determined such that, compared to a time since the shared memory's sending an invalidation request until the Acquire side processor's completing a process for invalidating the cache, longer is a time taken totally by the shared memory's sending the acknowledgement response in response to the Store instruction from the Release side processor, the Release side processor's writing a flag into the shared memory the predetermined time later, and the Acquire side processor's reading the flag, and

an invalidation request control unit configured to perform the process for invalidating the cache in accordance with the invalidation request from the shared memory,

wherein,

the shared memory sends the invalidation request to the Acquire side processor for invalidating the cache in the Acquire side processor, based on writing of data by the Release side processor,

the memory access control unit in the Release side processor issues StoreFence instruction if both of the store counter and the wait counter have come to indicate 0, and

the memory access control unit in the Acquire side processor issues a LoadFence instruction in response to the StoreFence instruction for guaranteeing completion of a cache invalidation in accordance with the invalidation request from the shared memory after completing the process for the cache invalidation.

2. The information processing device according to claim 1 , wherein:

the shared memory consists of a plurality of banks; and

each one of the plurality of banks comprises

a memory main body, and

a directory unit configured to send the invalidation request in response to writing of data into the memory main body.

3. A memory order guarantee method comprising:

based on writing of data from a Release side processor intending to write data, sending, to an Acquire side processor intending to read data, an invalidation request for its cache, using a shared memory;

issuing a StoreFence instruction, using the Release side processor, if both of a store counter and a wait counter have come to indicate 0;

increasing the value of the store counter if a Store instruction is issued to the shared memory, and decreasing if an acknowledgement response indicating correct reception of the Store instruction is received from the shared memory;

setting a value of the wait counter, the value representing a predetermined time if the store counter has come to indicate 0, and decreasing the value at the predetermined time, the predetermined time being determined such that, compared to a time since the shared memory's sending the invalidation request until the Acquire side processor's completing a process for invalidating the cache, longer is a time taken totally by the shared memory's sending the acknowledgement response in response to the Store instruction from the Release side processor, the Release side processor's writing a flag into the shared memory;

the predetermined time later, the Acquire side processor's reading the flag; and

in relation to the StoreFence instruction, by the Acquire side processor, issuing a LoadFence instruction for guaranteeing completion of a cache invalidation in accordance with the invalidation request from the shared memory, after completing the process for the cache invalidation.

4. The memory order guarantee method according to claim 3 , wherein:

the shared memory consists of a plurality of banks; and

each one of the plurality of banks sends the invalidation request in response to writing of data into its memory main body.

5. A readable non-volatile recording medium storing a program for causing a computer to execute:

based on writing of data from a Release side processor intending to write data, sending, to an Acquire side processor intending to read data, an invalidation request for its cache, using a shared memory;

issuing a StoreFence instruction, using the Release side processor, if both of a store counter and a wait counter have come to indicate 0;

increasing the value of the store counter if a Store instruction is issued to the shared memory, and decreasing if an acknowledgement response indicating correct reception of the Store instruction is received from the shared memory;

setting a value of the wait counter, the value representing a predetermined time if the store counter has come to indicate 0, and decreasing the value at the predetermined time, the predetermined time being determined such that, compared to a time since the shared memory's sending the invalidation request until the Acquire side processor's completing the process for invalidating the cache, longer is a time taken totally by the shared memory's sending the acknowledgement response in response to the Store instruction from the Release side processor, the Release side processor's writing a flag into the shared memory

the predetermined time later, and the Acquire side processor's reading the flag; and

in relation to the StoreFence instruction, by the Acquire side processor, issuing a LoadFence instruction for guaranteeing completion of the cache invalidation in accordance with the invalidation request from the shared memory, after completing a process for the cache invalidation.

6. The readable non-volatile recording medium storing a program according to claim 5 , wherein:

the shared memory consists of a plurality of banks; and

the program causes the computer to execute a process in which each one of the plurality of banks sends the invalidation request in response to writing of data into its memory main body.