Semiconductor device

1. A semiconductor device comprising:

a plurality of spin units individually including:

a memory cell configured to store a value of a single spin in an Ising model;

a memory cell configured to store an interaction coefficient expressing an interaction from another spin to the single spin;

a coefficient regulator configured to select one from a predetermined coefficient group at a probability proportional to a size of the interaction coefficient by comparing the interaction coefficient with a random number; and

an arithmetic circuit configured to perform an arithmetic operation to determine a subsequent state of the spin according to the selected coefficient; and

a random number generator configured to supply the random number to the plurality of the spin units.

2. The semiconductor device according to claim 1 ,

wherein the random number supplied to the plurality of the spin units is a random pulse train.

3. The semiconductor device according to claim 2 ,

wherein the interaction coefficient is a signed integer of three bits or greater.

4. The semiconductor device according to claim 1 ,

wherein a product of the coefficient selected at the coefficient regulator and a value of an adjacent spin is computed and inputted to a majority logic circuit.

5. The semiconductor device according to claim 4 ,

wherein the interaction coefficient is a signed integer of three bits or greater.

6. The semiconductor device according to claim 1 ,

wherein the interaction coefficient is a signed integer of three bits or greater.

7. The semiconductor device according to claim 1 ,

wherein the random number generator includes a bit controller configured to variably control a bit probability and output a random pulse train; and

each time the spin unit performs the arithmetic operation a predetermined number of times, the bit controller in turn decreases a bit probability of a random pulse train to be outputted when an arithmetic operation is performed a subsequent predetermined number of times.

8. The semiconductor device according to claim 7 ,

wherein one bit of a random pulse train outputted from the bit controller is supplied to the spin units; and

a random number in width of a plurality of bits is generated by passing the random pulse train through a delay device in the spin units and is inputted to the coefficient regulator.

9. A semiconductor device comprising:

a plurality of spin units individually including:

a memory cell configured to store values of spins in an Ising model;

a memory cell configured to store an interaction coefficient from an adjacent spin that exerts an interaction on the spin;

a memory cell configured to store an external magnetic field coefficient of the spin; and

an interaction circuit configured to determine a subsequent state of the spin,

wherein the memory cell storing the interaction coefficient and the memory cell storing the external magnetic field coefficient are formed of a shift register that stores a simulated coefficient string generated in advance, shifts the stored simulated coefficient string, and in turn outputs a leading simulated coefficient in performing an interaction to determine a subsequent state of a spin of the spin units from a value of a spin from an adjacent spin unit, an interaction coefficient, and an external magnetic field coefficient.

10. The semiconductor device according to claim 9 ,

wherein the memory cell storing the interaction coefficient and the memory cell storing the external magnetic field coefficient are formed of a memory cell group including a selector that stores a simulated coefficient string generated in advance, selects the stored simulated coefficient string according to a record of a counter, and in turn outputs the simulated coefficient in performing an interaction to determine a subsequent state of a spin of the spin units from a value of a spin from an adjacent spin unit, an interaction coefficient, and an external magnetic field coefficient.