IP Library Granted Patent US 9,607,710
Granted Patent B2
US 9,607,710 · App. 14/936,340 · Granted Mar 28, 2017

Read-threshold calibration in a solid state storage system

Inventors: Fan Zhang (Fremont, CA); June Lee (Sunnyvale, CA)
Assignee: SK hynix memory solutions Inc.
G11C16/3427G11C11/5642G11C16/26G11C29/021G11C29/028G11C16/34
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Quick Facts
Patent No.
US 9,607,710
App. No.
14/936,340
Granted
Mar 28, 2017
Kind
B2
Abstract

A read-threshold calibration method in a solid state storage system including measuring a threshold voltage distribution of solid state storage elements; determining a threshold voltage; decoding data according to the determined threshold voltage; filtering the threshold voltage distribution of solid state storage elements with a predetermined filter length when the decoding fails; changing the filter length; and repeating the determining, decoding, filtering, and changing steps with the changed filter length until the decoding is successful.

Claims (44)

1. A read-threshold calibration method in a solid state storage system, comprising:

measuring, with a controller, a threshold voltage distribution of solid state storage elements;

locating, with the controller, a first minimum point of the threshold voltage distribution;

estimating, with the controller, a first optimal read threshold based on the located first minimum point;

decoding, with the controller, data using the estimated first optimal read threshold;

if decoding fails:

removing, with the controller, an excessive number of minimum points from the threshold voltage distribution by filtering the threshold voltage distribution of the solid state storage elements;

locating, with the controller, a subsequent minimum point of the filtered threshold voltage distribution;

estimating, with the controller, a subsequent optimal read threshold based on the located subsequent minimum point; and

decoding, with the controller, the data that previously failed to decode using the estimated subsequent optimal read threshold.

2. The read-threshold calibration method in a solid state storage system according to claim 1 , wherein the excessive number of minimum points are removed from the threshold voltage distribution by filtering with a filter length in a range of two to eight.

3. The read-threshold calibration method in a solid state storage system according to claim 2 , further comprising changing the filter length if decoding fails.

4. The read-threshold calibration method in a solid state storage system according to claim 1 , wherein the measuring the threshold voltage distribution of solid state storage elements is performed by reading the solid state storage elements using a variety of read threshold voltages.

5. The read-threshold calibration method in a solid state storage system according to claim 1 , further comprising terminating the read-threshold calibration method when the decoding is successful.

6. The read-threshold calibration method in a solid state storage system according to claim 1 , wherein the determining a threshold voltage includes selecting the threshold voltage to reduce the number of read errors.

7. A system, comprising:

solid state storage elements; and

a storage controller suitable for:

measuring a threshold voltage distribution of the solid state storage elements;

locating a first minimum point of the threshold voltage distribution;

estimating a first optimal read threshold based on the located first minimum point;

decoding data using the estimated first optimal read threshold;

wherein, if decoding fails, the storage controller is further suitable for:

removing an excessive number of minimum points from the threshold voltage distribution by filtering the threshold voltage distribution of the solid state storage elements;

locating a subsequent minimum point of the filtered threshold voltage distribution;

estimating a subsequent optimal read threshold based on the located subsequent minimum point; and

decoding data using the estimated subsequent optimal read threshold.

8. The system according to claim 7 , wherein the excessive number of minimum points are removed from the threshold voltage distribution by filtering with a filter length in a range of two to eight.

9. The system according to claim 8 , wherein the storage controller is further suitable for changing the filter length if decoding fails.

10. The system according to claim 7 , wherein the read-threshold calibrator is suitable for measuring the threshold voltage distribution of solid state storage elements by reading the solid state storage elements using a number of read threshold voltages.

11. The system according to claim 7 , wherein the storage controller is further suitable for terminating operation if the decoding is successful.

12. The system according to claim 7 , wherein the read-threshold calibrator is suitable for determining the threshold voltage by selecting the threshold voltage to reduce the number of read errors.

13. A computer implemented process for calibrating a read threshold, the computer implemented process being implemented in a non-transitory computer readable storage medium and comprising computer instructions for:

measuring a threshold voltage distribution of solid state storage elements;

locating a first minimum point of the threshold voltage distribution;

estimating a first optimal read threshold based on the located first minimum point;

decoding data using the estimated first optimal read threshold;

if decoding fails:

removing an excessive number of minimum points from the threshold voltage distribution by filtering the threshold voltage distribution of the solid state storage elements;

locating a subsequent minimum point of the filtered threshold voltage distribution;

estimating a subsequent optimal read threshold based on the located subsequent minimum point; and

decoding the data that previously failed to decode using the estimated subsequent optimal read threshold.

14. The computer implemented process according to claim 13 , wherein the excessive number of minimum points are removed from the threshold voltage distribution by filtering with a filter length in a range of two to eight.

15. The computer implemented process according to claim 13 , wherein the instructions further comprises terminating operation if the decoding is successful.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 15, 2017
From: SK HYNIX MEMORY SOLUTIONS INC.
To: SK HYNIX INC.
Reel/Frame 044899/0443 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 15, 2015
From: ZHANG, FAN; LEE, JUNE
To: SK HYNIX MEMORY SOLUTIONS INC.
Reel/Frame 037294/0100 →
Continuity (2)
Provisional Application 62077604 · Nov 10, 2014
Related Publication 20160133334A1 · May 12, 2016