High electron mobility transistor with periodically carbon doped gallium nitride
A method for forming a high electron mobility transistor (HEMT) device with a plurality of alternating layers of one or more undoped gallium nitride (GaN) layers and one or more carbon doped gallium nitride layers (c-GaN), and an HEMT device formed by the method is disclosed. In one embodiment, the method includes forming a channel layer stack on a substrate, the channel layer stack having a plurality of alternating layers of one or more undoped gallium nitride (GaN) layers and one or more carbon doped gallium nitride layers (c-GaN). The method further includes forming a barrier layer on the channel layer stack. In one embodiment, the channel layer stack is formed by growing each of the one or more undoped gallium nitride (GaN) layers in growth conditions that suppress the incorporation of carbon in gallium nitride, and growing each of the one or more carbon doped gallium nitride (c-GaN) layers in growth conditions that promote the incorporation of carbon in gallium nitride.
1. A method of forming a high electron mobility transistor device, the method comprising:
providing a substrate;
forming a channel layer stack on the substrate having at least four alternating layers of gallium nitride layers and carbon doped gallium nitride layers; and
forming a barrier layer on the channel layer stack,
wherein the high electron mobility transistor device has a lateral breakdown voltage between 1000V and 1280V or a vertical breakdown voltage between 1000V and 1180V.
2. The method according to claim 1 , wherein forming the channel layer stack comprises
growing each of the gallium nitride layers in first growth conditions such that carbon incorporation in the gallium nitride is suppressed, and
growing each of the carbon doped gallium nitride layers in second growth conditions such that carbon incorporation in the gallium nitride is promoted.
3. The method according to claim 1 , wherein forming the channel layer stack comprises
forming each of the gallium nitride layers with a carbon concentration less than 1E 18 Atoms/cm 3 ; and
forming each of the carbon doped gallium nitride layers having a carbon concentration of greater than 1E 18 Atoms/cm 3 .
4. The method according to claim 2 , wherein
growing each of the gallium nitride layers comprises providing the first growth conditions comprise a low growth rate and a high ratio of group-V precursors to group-III precursors, and
growing each of the carbon doped gallium nitride layers comprises providing a high growth rate and a low ratio of group-V precursors to group-III precursors.
5. The method according to claim 4 , wherein
the low growth rate for growing each of the gallium nitride layers is greater than 0.1 μm/hr and less than 5 μm/hr, and
the high growth rate for growing each of the carbon doped gallium nitride layers is greater than 5 μm/hr and less than 10 μm/hr.
6. The method according to claim 5 , wherein the high growth rate for growing each of the carbon doped gallium nitride layers is about 15 to 20 times greater than the low growth rate for growing each of the gallium nitride layers.
7. The method according to claim 4 , wherein the high ratio for growing each of the gallium nitride layers is greater than 100:1 and less than 10000:1, and the low ratio for growing each of the carbon doped gallium nitride layers is greater than 10:1 and less than 200:1.
8. The method according to claim 4 , wherein the first and second growth conditions for growing each of the gallium nitride layers and each of the carbon doped gallium nitride layers further comprise a growth temperature and a growth pressure.
9. The method according to claim 8 , wherein the growth temperature for growing each of the gallium nitride layers and each of the carbon doped gallium nitride layers is greater than 750 C and less than 1000 C, and
wherein the growth pressure for growing each of the gallium nitride layers and each of the carbon doped gallium nitride layers is greater than 35 Torr and less than 700 Torr.
10. The method according to claim 1 , wherein forming the channel layer stack comprises
growing each of the gallium nitride layers to a thickness greater than lnm and less than 200 nm, and
growing each of the carbon doped gallium nitride layers to a thickness greater than lnm and less than 500 nm.
11. The method according to claim 1 , wherein forming the channel layer stack comprises growing each one of the gallium nitride layers and each one of the carbon doped gallium nitride layers such that the ratio of the thickness of each of the carbon doped gallium nitride layers to the thickness of each of the gallium nitride layers is greater than 1:3 and less than 3:1.
12. The method according to claim 1 , further comprising:
forming a source electrode electrically coupled to the barrier layer;
forming a drain electrode electrically coupled to the barrier layer; and
forming a gate electrode electrically coupled to the barrier layer between the source and drain electrodes,
wherein the source and drain electrodes form an ohmic connection with the barrier layer, and the gate electrode forms a non-ohmic connection with the barrier layer.
13. The method according to claim 1 , wherein the barrier layer comprises aluminum gallium nitride.
14. The method according to claim 1 , further comprising:
forming a buffer layer between the substrate and the channel layer stack.
15. A high electron mobility transistor device comprising:
a substrate;
a channel layer stack on the substrate having at least four alternating layers of gallium nitride layers and carbon doped gallium nitride layers; and
a barrier layer on the channel layer stack,
wherein the high electron mobility transistor device has a lateral breakdown voltage between 1000V and 1280V or a vertical breakdown voltage between 1000V and 1180V.
16. The high electron mobility transistor device of claim 15 , wherein each of the gallium nitride layers have a carbon concentration less than 1E 18 Atoms/cm 3 and each of carbon doped gallium nitride layers have a carbon concentration of greater than 1E 18 Atoms/cm 3 .
17. The high electron mobility transistor device of claim 15 , wherein each of the gallium nitride layers have a thickness greater than lnm and less than 200 nm, and each of the carbon doped gallium nitride layers have a thickness greater than lnm and less than 500 nm.
18. The high electron mobility transistor device of claim 15 , wherein the ratio of the thickness of each of the carbon doped gallium nitride layers to the thickness of each of the gallium nitride layers is greater than 1:3 and less than 3:1.
19. The high electron mobility transistor device of claim 15 , further comprising:
a source electrode electrically coupled to the barrier layer;
a drain electrode electrically coupled to the barrier layer; and
a gate electrode electrically coupled to the barrier layer between the source and drain electrodes,
wherein the source and drain electrodes form an ohmic connection with the barrier layer, and the gate electrode forms a non-ohmic connection with the barrier layer.
20. The high electron mobility transistor device according to claim 15 , wherein the barrier layer comprises aluminum gallium nitride.
21. The high electron mobility transistor device according to claim 15 , further comprising:
a buffer layer between the substrate and the channel layer stack.
22. The method of claim 1 , wherein an uppermost layer of the channel layer stack is a gallium nitride layer.
23. The method of claim 1 , wherein a lowermost layer of the channel layer stack is a gallium nitride layer.
24. The method of claim 1 , wherein both an uppermost layer and a lowermost layer of the channel layer stack are gallium nitride layers.
25. The high electron mobility transistor device of claim 15 , wherein an uppermost layer of the channel layer stack is a gallium nitride layer.
26. The high electron mobility transistor device of claim 15 , wherein a lowermost layer of the channel layer stack is a gallium nitride layer.
27. The high electron mobility transistor device of claim 15 , wherein both an uppermost layer and a lowermost layer of the channel layer stack are gallium nitride layers.
28. The method of claim 1 , wherein the high electron mobility transistor device has a lateral breakdown voltage between 1000V and 1280V and a vertical breakdown voltage between 1000V and 1180V.
29. The high electron mobility transistor device of claim 15 , wherein the high electron mobility transistor device has a lateral breakdown voltage between 1000V and 1280V and a vertical breakdown voltage between 1000V and 1180V.