Nanowire device and method of manufacturing the same

1. A method of manufacturing a nanowire device, comprising:

providing a substrate, wherein the substrate comprises a pair of support pads, a recess disposed between the support pads, a second insulating layer disposed on the support pads, a third insulating layer disposed on a bottom of the recess, and at least one nanowire suspended between the support pads at a top portion of the recess;

forming a first insulating layer on the nanowire;

depositing a dummy gate material over the substrate on the first insulating layer, and patterning the dummy gate material to form a dummy gate structure surrounding a channel region, wherein the dummy gate structure comprises a dummy gate and the first insulating layer, and wherein the first insulating layer is disposed between the dummy gate and the channel region;

forming a first oxide layer on laterally opposite sidewalls of the dummy gate;

forming a second oxide layer on laterally opposite ends of the channel region, wherein the thickness of the first oxide layer is greater than the thickness of the second oxide layer;

removing a portion of the first oxide layer and the entire second oxide layer, so as to expose the laterally opposite ends of the channel region; and

extending the nanowire on the laterally opposite ends of the channel region to the respective support pads, so as to form a source region and a drain region.

2. The method according to claim 1 , wherein patterning the dummy gate material further comprises:

forming a hard mask layer on the dummy gate material;

patterning the hard mask layer to define a gate region; and

etching the dummy gate material, the nanowire, and the first insulating layer surrounding the nanowire through the patterned hard mask layer to a surface of the third insulating layer.

3. The method according to claim 2 , wherein the nanowire includes germanium or Group III-V semiconductor materials, and

the dummy gate material includes polycrystalline silicon germanium (SiGe), amorphous SiGe, polycrystalline silicon, or amorphous silicon.

4. The method according to claim 2 , wherein the nanowire includes monocrystalline silicon, and

the dummy gate material includes polycrystalline silicon germanium (SiGe) or amorphous SiGe.

5. The method according to claim 2 , wherein the nanowire device includes a plurality of the nanowires, and

some of the nanowires include germanium or Group III-V semiconductor materials, the remaining nanowires include monocrystalline silicon, and the dummy gate material includes polycrystalline SiGe or amorphous SiGe.

6. The method according to claim 2 , wherein the nanowire on the laterally opposite ends of the channel region is epitaxially doped in-situ while the nanowire is being extended to the respective support pads.

7. The method according to claim 2 , wherein forming the source region and the drain region further comprises:

performing at least one ion implantation step after forming the source region and the drain region, wherein the ion implantation step includes forming a lightly doped drain (LDD) or a dopant implantation of the source and drain regions.

8. The method according to claim 1 , further comprising:

performing a self-aligned silicide process after forming the source region and the drain region, so as to form a silicide on the dummy gate, the source region, and the drain region.

9. The method according to claim 1 , further comprising:

forming a silicon nitride layer on respective top and bottom surfaces of the source region and the drain region, and on the laterally opposite sidewalls of the dummy gate;

forming an interlayer dielectric layer over the substrate on the silicon nitride layer;

performing chemical mechanical polishing to expose the dummy gate;

removing the dummy gate and the first insulating layer to form a trench; and

forming a gate structure.

10. The method according to claim 9 , wherein forming the gate structure further comprises:

forming an interfacial oxide layer on a surface of the channel region;

forming a high-k gate dielectric layer on the interfacial oxide layer, and on the sidewalls and bottom of the trench;

forming a gate electrode to surround the channel region and cover the high-k gate dielectric layer; and

performing chemical mechanical polishing to expose the gate electrode.

11. The method according to claim 9 , wherein forming the gate structure further comprises:

forming an interfacial oxide layer on a surface of the channel region, and on the sidewalls and bottom of the trench;

forming a high-k gate dielectric layer on the interfacial oxide layer;

forming a gate electrode to surround the channel region and cover the high-k gate dielectric layer; and

performing chemical mechanical polishing to expose the gate electrode.