Detection circuit for relative error voltage
A detection circuit for a relative error voltage, including: a first current mirror, a second current mirror, a third current mirror, a current sink and resistors R 1 , R 2 and R 3 . A voltage signal to be detected V 1 accesses the first current mirror via the resistor R 2 , and a voltage signal to be detected V 2 accesses the second current mirror via the resistor R 3 ; a mirrored-end of the first current mirror is connected to the current sink, and a mirroring-end thereof is connected to a mirrored-end of the third current mirror; a mirrored-end of the second current mirror is connected to the current sink, and a mirroring-end thereof is connected to a mirroring-end of the third current mirror; the current sink is grounded via the resistor R 1 ; and the third current mirror converts double-ended currents of the first and the second current mirrors to single-ended currents to output as voltage signals.
1. A detection circuit for a relative error voltage, comprising: a first current mirror, a second current mirror, a third current mirror, a current sink and resistors R 1 , R 2 and R 3 ; wherein,
a voltage signal to be detected V 1 accesses the first current mirror via the resistor R 2 , and a voltage signal to be detected V 2 accesses the second current mirror via the resistor R 3 ;
a mirrored end of the first current mirror is connected to the current sink, and a mirroring end of the first current mirror is connected to a mirrored end of the third current mirror; a mirrored end of the second current mirror is connected to the current sink, and a mirroring end of the second current mirror is connected to a mirroring end of the third current mirror; and
the current sink is grounded via the resistor R 1 ; and the third current mirror converts double-ended currents of the first current mirror and the second current mirror to single-ended currents to output as voltage signals.
2. The detection circuit for a relative error voltage according to claim 1 , wherein, the current sink limits an influent current as: I 1 =K*Vref/R 1 ;
wherein, K is a proportion coefficient (K is a constant not equal to zero), and Vref is a reference voltage with a zero-temperature coefficient.
3. The detection circuit for a relative error voltage according to claim 2 , wherein,
when the detection circuit for the relative error voltage is in a balance state, a voltage difference between the voltage signals to be detected is: V 1 −V 2 =I 1 *(R 2 −R 3 ); if the R 2 is equal to the R 3 , then an output logic level is reversed when the voltage difference between the V 1 and the V 2 is not zero; and if the R 2 is not equal to the R 3 , then the output logic level is reversed when the voltage difference between the V 1 and the V 2 reaches a set value.
4. The detection circuit for a relative error voltage according to claim 1 , wherein, resistance types of the resistors R 1 , R 2 and R 3 are the same.
5. The detection circuit for a relative error voltage according to claim 1 , wherein, the resistors R 1 , R 2 and R 3 are variable resistors.
6. The detection circuit for a relative error voltage according to claim 5 , wherein, the resistors R 1 , R 2 and R 3 are variable resistors adjusted through a logic switch.
7. The detection circuit for a relative error voltage according to claim 1 , wherein,
both the first current mirror and the second current mirror are constituted of two common-source common-gate P-type field effect transistors, or, both the first current mirror and the second current mirror are constituted of two common-emitter common-base PNP-type triodes, and a grid and a drain of a transistor at a mirrored end, or a base and a collector of a triode at a mirrored end, are short-circuited as a diode structure; and
the third current mirror is constituted of two common-source common-gate N-type field effect transistors, or, is constituted of two common-emitter common-base NPN-type triodes, and a grid and a drain of a transistor at a mirrored end, or a base and a collector of a triode at a mirrored end, are short-circuited as a diode structure.
8. The detection circuit for a relative error voltage according to claim 7 , wherein,
the voltage signal to be detected V 1 accesses a source or an emitter of the first current mirror through the resistor R 2 , and the voltage signal to be detected V 2 accesses a source or an emitter of the second current mirror through the resistor R 3 .
9. The detection circuit for a relative error voltage according to claim 2 , wherein, the resistors R 1 , R 2 and R 3 are variable resistors.
10. The detection circuit for a relative error voltage according to claim 3 , wherein, the resistors R 1 , R 2 and R 3 are variable resistors.
11. The detection circuit for a relative error voltage according to claim 4 , wherein, the resistors R 1 , R 2 and R 3 are variable resistors.
12. The detection circuit for a relative error voltage according to claim 9 , wherein, the resistors R 1 , R 2 and R 3 are variable resistors adjusted through a logic switch.
13. The detection circuit for a relative error voltage according to claim 10 , wherein, the resistors R 1 , R 2 and R 3 are variable resistors adjusted through a logic switch.
14. The detection circuit for a relative error voltage according to claim 11 , wherein, the resistors R 1 , R 2 and R 3 are variable resistors adjusted through a logic switch.