IP Library Granted Patent US 9,620,601
Granted Patent B2
US 9,620,601 · App. 14/321,366 · Granted Apr 11, 2017

Contact structures and methods of forming the same

Inventors: Yu-Hung Lin (Taichung, TW); Sheng-Hsuan Lin (Zhubei, TW); Chih-Wei Chang (Hsin-Chu, TW); You-Hua Chou (Hsin-Chu, TW); Chia-Lin Hsu (Tainan, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L29/41791H01L21/28518H01L21/76843H01L21/76855H01L23/485H01L29/66795H01L21/0262H01L21/02529H01L21/02532H01L21/02576H01L23/53266H01L2924/0002
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,620,601
App. No.
14/321,366
Granted
Apr 11, 2017
Kind
B2
Abstract

Embodiments of the present disclosure include contact structures and methods of forming the same. An embodiment is a method of forming a semiconductor device, the method including forming a contact region over a substrate, forming a dielectric layer over the contact region and the substrate, and forming an opening through the dielectric layer to expose a portion of the contact region. The method further includes forming a metal-silicide layer on the exposed portion of the contact region and along sidewalls of the opening; and filling the opening with a conductive material to form a conductive plug in the dielectric layer, the conductive plug being electrically coupled to the contact region.

Claims (51)

1. A method of forming a semiconductor device, the method comprising:

forming a contact region over a substrate;

forming a dielectric layer over the contact region and the substrate;

forming an opening through the dielectric layer to expose a portion of the contact region;

forming a metal-silicide layer on the exposed portion of the contact region and along sidewalls of the opening, wherein the forming the metal-silicide layer comprises:

forming a silicon-containing capping layer along the exposed portion of the contact region, the sidewalls of the opening, and over the dielectric layer;

forming a metal layer over the silicon-containing capping layer in the opening and over the dielectric layer;

forming a glue layer over the metal layer in the opening and over the dielectric layer; and

performing a silicidation process to react at least portions of the silicon-containing capping layer and the metal layer to form the metal-silicide layer; and

filling the remaining portion of the opening over the glue layer and the metal-silicide layer with a conductive material to form a conductive plug in the dielectric layer, the conductive plug being electrically coupled to the contact region.

2. The method of claim 1 , wherein the forming the silicon-containing capping layer comprises silicon, germanium, silicon germanium, silicon carbide, silicon phosphide, or a combination thereof.

3. The method of claim 1 , wherein the metal layer comprises nickel, cobalt, titanium, tungsten, or a combination thereof.

4. The method of claim 1 , wherein the glue layer comprises titanium nitride, tantalum nitride, or a combination thereof.

5. The method of claim 1 , wherein the performing the silicidation process comprises:

performing an annealing process on the substrate at temperature from about 100° C. to about 900° C. with process gases including Ar, N 2 , or a combination thereof and at a pressure from 770 Torr to about 1000 Torr.

6. The method of claim 1 , wherein the forming the metal-silicide layer on the exposed portion of the contact region and along the sidewalls of the opening consumes at least a portion of the contact region.

7. The method of claim 1 further comprising:

planarizing the conductive material to form the conductive plug, wherein after the planarizing step a top surface of the conductive plug is substantially coplanar with a top surface of the dielectric layer.

8. The method of claim 1 , where the substrate is a semiconductor fin for a fin field-effect transistor (FinFET) and the contact region is a source/drain region for the FinFET, and wherein the forming the contact region comprises:

etching a recess in semiconductor fin;

epitaxially growing a semiconductor material in the recess; and

doping the semiconductor material with at least one dopant to form a source/drain region.

9. The method of claim 1 , wherein the contact region comprises silicon, silicon germanium, silicon phosphide, silicon carbide, or a combination thereof.

10. The method of claim 1 , wherein the metal-silicide layer extends along substantially the sidewalls of the opening from a top surface of the contact region to a top surface of the dielectric layer.

11. The method of claim 1 , wherein the metal-silicide layer has a first thickness along the contact region and a second thickness along the sidewalls of the opening, the first thickness being from about 30 Angstroms (Å) to about 300 Å and the second thickness being from about 3 Å to about 30 Å.

12. The method of claim 1 , wherein the glue layer is formed after the metal layer.

13. A method of forming a contact structure, the method comprising:

forming a contact layer over a substrate;

depositing a dielectric layer over the contact layer and the substrate;

patterning the dielectric layer to form an opening through the dielectric layer, at least a portion of the contact layer being exposed in the opening;

depositing a capping layer in the opening along the exposed contact layer and sidewalls of the dielectric layer and over the dielectric layer;

depositing a metal layer over the capping layer in the opening and over the dielectric layer;

depositing a glue layer over the metal layer in the opening and over the dielectric layer;

after depositing the glue layer, annealing the capping layer and the metal layer to form a metal-silicide layer in the opening along the contact layer and the sidewalls of the dielectric layer and over the dielectric layer; and

after forming the metal-silicide layer, filling a conductive material on the glue layer in the opening and over the dielectric layer.

14. The method of claim 13 further comprising:

performing a planarization process to forming a conductive plug in the dielectric layer, the planarization process removing the conductive material, the glue layer, and metal-silicide layer over the dielectric layer.

15. The method of claim 13 , wherein after the annealing the capping layer and the metal layer to form the metal-silicide layer, a portion of the metal layer remains unreacted and is interposed between the metal-silicide layer and the glue layer.

16. The method of claim 15 , wherein the portion of the metal layer remaining unreacted has a thickness from about 3 Angstroms (Å) to about 30 Å.

17. The method of claim 13 , wherein the capping layer has a substantially same material composition as the contact layer.

18. A method of forming a contact structure, the method comprising:

forming a contact region in a substrate;

forming a dielectric layer over the contact region;

forming an opening in the dielectric layer to expose at least a surface of the contact region;

conformally depositing a silicon-containing capping layer along the exposed surface of the contact region and sidewalls of the opening;

conformally depositing a metal layer over the silicon-containing capping layer in the opening;

conformally depositing a glue layer over the metal layer in the opening;

annealing the silicon-containing capping layer and the metal layer to form a metal-silicide layer in the opening along the contact region and the sidewalls of the dielectric layer; and

after forming the metal-silicide layer, filling a conductive material in the opening over the glue layer and over the dielectric layer.

19. The method of claim 18 , wherein the step of annealing the silicon-containing capping layer and the metal layer is performed after the step of conformally depositing a glue layer on the metal layer in the opening.

20. The method of claim 18 , wherein the metal-silicide layer has a surface extending below a top surface of the contact region.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 1, 2014
From: LIN, YU-HUNG; LIN, SHENG-HSUAN; CHANG, CHIH-WEI; CHOU, YOU-HUA; HSU, CHIA-LIN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 033224/0823 →
Continuity (1)
Related Publication 20160005824A1 · Jan 7, 2016